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mixed-signal front-end (mxfe ? ) baseband transceiver for broadband applications AD9863 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features receive path in cludes dua l 12 - b it, 50 msps a n alog-to-digital converters with internal or ex ternal refer e nce transmit path i n cludes dual 1 2 -bit, 200 msp s digital-to- analog converters with 1, 2, or 4 interpol ation and programmable gain control internal clock distribution block includes a programmable phase-locked l oop and timing generation circuitry, allowing single-reference clock operation 24-pin flexible i/o data interfa c e allows vario u s interl eave d or noninterleaved data transf ers in half -dupl e x mode and interleaved dat a transfers in f u ll- duplex mod e configurable t h rough register programmabi lity or optionally limi ted programmability through mode pins independent r x and tx power - down control pins 64-lea d lfcsp package (9 mm 9 mm footprint) applic ati o ns b r o a dband access b r o a dband lan communications (modems) func tio n a l block di agram 03604-0-070 data mux and latch data latch and demux i/o interface configuration block AD9863 i/o interface control flexible i/o bus [0:23] rx data tx data adc vin+a vin ? a adc vin+b vin ? b low-pass interpolation filter dac iout+ a iout? a dac iout+b iout? b clkin1 adc clock dac clock pll clkin2 clock generation block fi g u r e 1 . general description the AD9863 is a mem b er o f the mxfe fa mil y a g r o u p o f in teg r a t e d con v er t e rs fo r t h e co mm unic a t io n s ma rk et. th e AD9863 in t e g r a t es d u al 12-b i t analog-t o-dig i t a l co n v er t e rs (ad c ) a nd d u a l 12-b i t digi t a l-to-a nalog co n v er t e r s (t xd a c ?). the ad986 3 ad cs a r e o p t i mized f o r ad c s a m p lin g o f 50 ms p s a nd les s . the du al txdacs operate at speeds u p to 200 mhz an d i n clud e a b y passabl e 2 or 4 interpola t io n filter. th e AD9863 is optimized for high pe rformance, lo w power, and sm all form f a ctor to provid e a cost-effective so lution for the br o a db a nd co m m un ica t io ns m a r k et. the AD9863 us es a sin g le in p u t c l o c k p i n (clkin) o r tw o inde p e n d e n t clo c ks fo r t h e tx p a t h and t h e rx p a t h . th e ad c an d txd a c clo c ks are ge ner a te d wi th in a ti mi n g gener a tio n block th at provid es user program m able options such as d i vid e circuits, pl l multipliers, and s w itc h es. a flexible, bidir e ctional 24-bit i / o bus accommodate s a v a riety of custom d i gital back e n d s or open market dsps. in half-duplex s y stems, the in terface supports 24-bit parallel transfers or 12-bit interleaved tran sfers. i n full-duplex syste m s, the i n t e rface su pports a 12-bi t i n terle a ve d a d c bus a nd a 12-bit in terle a v e d txdac bus. th e flexibl e i/o bus reduce s pi n count, also redu cing the requ ired package s i ze on the AD9863 an d th e d e vic e t o whic h it co nn ects. the AD9863 c a n use either mo de pins or a serial programma- ble interfac e (spi) to configure the i n t e rface b u s, operate t h e adc i n a lo w p o wer mode , con f igure th e txd a c i n terpola t io n r a te, a n d co ntr o l adc a n d tx d a c po wer - do w n . t h e s p i provid es m o re programmab l e opti on s for b o th th e t x d a c p a t h (fo r ex ample, c o ar se an d fi ne g a i n co ntr o l a nd o ffset co ntr o l fo r channel matchi ng) and t h e ad c pat h (for example, t h e i n t e rnal duty cy cle sta b il izer a n d twos c o mplem e n t d a t a format). the AD9863 is packaged in a 6 4 -lead lfcsp (l ow profile, fine pitche d, c h ip sc ale pac kag e). the 64-le ad lfc s p footprint is only 9 mm 9 mm and is l e ss than 0.9 mm hig h , fitting into such tig h tly sp aced appl ications as pcmci a c a rds. 4 .com u datasheet
AD9863 rev. a| page 2 of 40 table of contents tx path specifications...................................................................... 3 rx path specifications...................................................................... 4 power specifications......................................................................... 5 digital specifications........................................................................ 5 timing specifications....................................................................... 6 absolute maximum ratings............................................................ 7 thermal resistance ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ........................................... 10 terminology .................................................................................... 17 theory of operation ...................................................................... 18 system block ............................................................................... 18 rx path block.............................................................................. 18 tx path block.............................................................................. 20 digital block................................................................................ 23 programmable registers............................................................ 33 clock distribution block .......................................................... 36 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 4/05rev. 0 to rev. a changes to ordering guide .......................................................... 40 11/03 revision 0: initial version 4 .com u datasheet
AD9863 r e v. a | pa ge 3 o f 4 0 tx path specifications fd a c = 200 ms ps; 4 in ter p ola t io n; rs et = 4.02 k?; dif f er en tial lo ad r e sis t an ce o f 100 ? 1 ; txpga = 20 db; a v d d = d v dd = 3.3 v , u n l e ss ot he r w i s e no te d. table 1. p a r a m e t e r t e m p t e s t leve l m i n t y p m a x u n i t tx path gene r al r e s o l u t i o n f u l l i v 1 2 b i t s maximum dac update rate full iv 200 mhz maximum full-s c ale output current full iv 20 ma full-scale error full v 1% gain mismatch error 25c iv ? 3.5 + 3 . 5 % f s offset mismatch error full iv ? 0.1 + 0 . 1 % f s reference voltage full v 1.23 v output capacitance full v 5 pf phase noise (1 khz offset, 6 mhz tone) 25c v ? 115 d b c / h z output voltage compli ance ran g e full iv ? 1.0 + 1 . 0 v txpga gain range full v 20 db txpga step size full v 0.10 db tx path dyna mic perfor m a n ce (i out f s = 20 ma; f ou t = 1 m h z) s n r f u l l i v 7 0 . 8 7 1 . 6 d b s i n a d f u l l i v 6 4 . 3 7 1 d b t h d f u l l i v ? 79 ? 66.3 dbc sfdr, wide band (dc to nyquist) full iv 68.5 77 dbc sfdr, narrow band (1 mhz win d ow) full iv 72.8 81 dbc 1 see figure 2 for description of the tx dac termination sc heme. 03604-0-071 txdac 50 ? 50 ? f i g u re 2. d i ag r a m sho w ing t e r m i n at i o n of 1 0 0 ? d i f f e r e nt ia l l oad f o r s o me t x da c m e as u r e m ent s 4 .com u datasheet
AD9863 rev. a| page 4 of 40 rx path specifications f adc = 50 msps; internal reference; differential analog inputs, adc_avdd = dvdd = 3.3 v, unless otherwise noted. table 2. parameter temp test level min typ max unit rx path general resolution full v 12 bits maximum adc sample rate full iv 50 msps gain mismatch error full v 0.2 % fs offset mismatch error full v 0.1 % fs reference voltage full v 1.0 v reference voltage (reftCrefb) error full iv ?30 6 +30 mv input resistance (differential) full v 2 k? input capacitance full v 5 pf input bandwidth full v 30 mhz differential analog input voltage range full v 2 v p-p differential rx path dc accuracy integral nonlinearity (inl) 25c v 0.75 lsb differential nonlinearity (dnl) 25c v 0.75 lsb aperture delay 25c v 2.0 ns aperture uncertainty (jitter) 25c v 1.2 ps rms input referred noise 25c v 250 v AD9863 rx path dynamic performance (v in = C0.5 dbfs; f in = 10 mhz) snr full v 67 dbc sinad full v 65.5 dbc thd (second to ninth harmonics) full iv ?73 ?66.6 dbc sfdr, wide band (dc to nyquist) full iv 68.3 74 dbc crosstalk between adc inputs full v 80 db 4 .com u datasheet
AD9863 rev. a | page 5 of 40 power specifications analog and digital supplies = 3.3 v; f clkin1 = f clkin2 = 50 mhz; pll 4 setting; normal timing mode. table 3. parameter temp test level min typ max unit power supply range analog supply voltage (avdd) full iv 2.7 3.6 v digital supply voltage (dvdd) full iv 2.7 3.6 v driver supply voltage (drvdd) full iv 2.7 3.6 v analog supply currents tx path (20 ma full-scale outputs) full v 70 ma tx path (2 ma full-scale outputs) full v 20 ma rx path (50 msps) full v 103 ma rx path (50 msps, low power mode) full v 69 ma rx path (20 msps, low power mode) full v 55 ma tx path, power-down mode full v 2 ma rx path, power-down mode full v 5 ma pll full v 12 ma digital supply currents tx path, 1 interpolation, 50 msps dac update for both dacs, half-duplex 24 mode full v 20 ma tx path, 2 interpolation, 100 msps dac update for both dacs, half-duplex 24 mode full v 50 ma tx path, 4 interpolation, 200 msps dac update for both dacs, half-duplex 24 mode full v 80 ma rx path digital, half-duplex 24 mode full v 15 ma digital specifications table 4. parameter temp test level min typ max unit logic levels input logic high voltage, v ih full iv drvdd ? 0.7 v input logic low voltage, v il full iv 0.4 v output logic high voltage, v oh (1 ma load) full iv drvdd ? 0.6 v output logic low voltage, v ol (1 ma load) full iv 0.4 v digital pin input leakage current full iv 12 a input capacitance full iv 3 pf minimum reset low pulse width full iv 5 input clock cycles digital output rise/fall time full iv 2.8 4 ns 4 .com u datasheet
AD9863 rev. a| page 6 of 40 timing specifications table 5. parameter temp test level min typ max unit input clock clkin2 clock rate (pll bypassed) full iv 1 200 mhz pll input frequency full iv 16 200 mhz pll ouput frequency full iv 32 350 mhz txpath data setup time (hd24 mode, time required be fore data latching edge) full v 5 ns (see clock distribution block section) hold time (hd24 mode, time required after data latching edge) full v ?1.5 ns (see clock distribution block section) latency 1 interpolation (data in until peak output response) full v 7 dac clock cycles latency 2 interpolation (data in until peak output response) full v 35 dac clock cycles latency 4 interpolation (data in until peak output response) full v 83 dac clock cycles rxpath data output delay (hd24 mode, t od ) full v ?1.5 ns ( see clock distribution block section) latency full v 5 adc clock cycles table 6. explanation of test levels level description i 100% production tested. ii 100% production tested at 25 c and guaranteed by design and characterization at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25 c and guaranteed by design and characteri zation for industrial temperature range. 4 .com u datasheet
AD9863 r e v. a | pa ge 7 o f 4 0 absolute maximum ratings table 7. p a r a m e t e r r a t i n g electrical avdd voltage 3.9 v max drvdd voltage 3.9 v max analog input voltage ? 0.3 v to av dd + 0 . 3 v digital input voltage ? 0.3 v to dvdd ? 0.3 v digital output c u rrent 5 ma max environmenta l operating tem p erature range (ambient) ? 40 c to +85 c maximum junction temperature 150 c lead temperature (sol dering, 10 s e c) 300 c storage temperature range (ambient) ? 65 c to +150 c s t r e s s es a b o v e t h os e list e d u nde r t h e a b s o l u t e m a xim u m r a t i n g s ma y c a us e p e r m an en t da ma g e t o t h e de v i ce . this is a st re ss r a t i n g on l y ; f u nc t i on a l o p e r a t i o n of t h e d e v i c e at t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i ndic a t e d i n t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . thermal resistance 64-lead lfcs p (4-la y er bo a r d): ja = 24.2 (p addle s o lder ed t o g r o u nd p l an, 0 lp m a i r) ja = 30.8 (p addle n o t s o lder ed to g r o u n d p l an, 0 lpm a i r) esd caution esd (electrostatic discharge) se nsiti ve device . e l ectrostatic char ges as high as 4 000 v readily accumulate on the human body and tes t eq uipment and can dis c harge w i t h out detection. although this product features proprietary esd protection circ uitry, permanent dama ge may occur on dev i ces subj ected to high energy electrostatic di scharge s . t h erefore, proper esd precautions are recom m ended to avoid performan c e degradation or l o ss of functiona l ity. 4 .com u datasheet
AD9863 r e v. a| pa g e 8 of 40 pin conf iguration and fu nction descriptions 03604-0-072 iface2 17 iface3 18 u1 1 19 u1 0 20 u9 21 u8 22 u7 23 u6 24 u5 25 u4 26 u3 27 u2 28 u1 29 u0 30 drv dd 31 d r vss 32 spi_c s 64 txpwrdwn 63 rx p w rdwn 62 adc_ av dd 61 re ft 60 adc_ av s s 59 vin + a 58 vin ? a 57 vr ef 56 vin ? b 55 vin + b 54 adc_ av s s 53 re fb 52 adc_ av dd 51 p l l_ av dd 50 pll_a vss 49 spi_dio 1 spi_clk 2 spi_sdo 3 a dc_lo_pw r 4 dvdd 5 dvss 6 avdd 7 iout? a 8 iout+a 9 agnd 10 refio 11 fsadj 12 agnd 13 iout+b 14 iout? b 15 avdd 16 clkin1 48 clkin2 47 reset 46 l0 45 l1 44 l2 43 l3 42 l4 41 l5 40 l6 39 l7 38 l8 37 l9 36 l10 35 l11 34 iface1 33 AD9863 top view (not to scale) f i gure 3. pin config ur ation ta ble 8. pi n f u nct i on d e s c ri pt i o ns pin no . name 1 d e s c r i p t i o n 2, 3 1 s p i _ d i o (interp1 ) spi: serial port data input. no spi: tx interp olation pin, msb. 2 s p i _ c l k (interp0 ) spi: serial port shift clock. no spi: tx interp olation pin, lsb. 3 s p i _ s d o (fd/ hd ) spi: 4-wire serial port data output. no spi: configur es full-du plex or half-duplex mode. 4 adc_lo_pwr adc low power mode enable. defined at power-up. 5, 31 dvdd, drv dd digital supply. 6, 32 dvss, drv dd digital ground. 7, 16, 50, 51, 61 avdd analog supply. 8, 9 iout ? a, iout+a dac a different ial output. 10, 13, 49, 53, 59 agnd, avs s analog ground. 11 refio tx dac band gap reference decoupling pin. 12 fsadj tx dac full-scale adjust pin. 14, 15 iout+b, iout?b dac b differenti a l output. spi: buffered c l kin. can be conf igured as system clock output. 1 7 i f a c e 2 (12/ 24 ) no spi: buffered clkin for fd; 1 2 / 24 configuration pin for hd24 or hd12. 1 8 i f a c e 3 c l o c k o u t p u t . 19 to 30 u11 to u0 upper data bit 11 to upper data bit 0. spi: txsync for fd; tx/ rx for hd24, hd12, or clone. 3 3 i f a c e 1 no spi: fd >> txsync; hd24 or hd12: tx/ rx . clon e mode requires a serial port interface. 34 to 45 l11 to l0 lower data bit 11 to lower data bit 0. 46 reset chip reset when low. 47 clkin2 clock in put 2. 48 clkin1 clock in put 1. 4 .com u datasheet
AD9863 rev. a | page 9 of 40 pin no. name 1 description 2, 3 52 refb adc bottom reference. 54, 55 vin+b, vin?b adc b differential input. 56 vref adc band gap reference. 57, 58 vin?a, vin+a adc a differential input. 60 reft adc top reference. 62 rxpwrdwn rx analog power-down control. 63 txpwrdwn tx analog power-down control. 64 spi_cs spi: serial port chip select. at power-up or reset, this must be high. no spi: tie low to disable spi and use mode pins. this pin must be tied low. 1 underlined pin names and descript ions apply when the device is co nfigured without a serial port interface, referred to as no s pi mode. 2 some pin descriptions depend on whether a serial port is used (spi mode) or not (no spi mode), indicated by the labels spi and no spi. 3 some pin descriptions depend on the inte rface configuration: full-duple x (fd), half-duplex interlea ved data (hd12), half-duple x parallel data (hd24), and a half-duplex interface similar to the ad9860 and ad9862 data interface called clon e mode (clone). clone mode re quires a serial port interfac e. 4 .com u datasheet
AD9863 r e v. a| pa g e 10 of 4 0 typical perf orm ance cha r acte ristics 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-001 frequency (mhz) amp l itude (dbfs ) f i gure 4. ad 9863 rx p a th sing le - t on e fft of rx ch anne l b p a th d i giti zing 2 m h z t o ne 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-002 frequency (mhz) amp l itude (dbfs ) f i gure 5. ad 9863 rx p a th sing le - t on e fft of rx ch anne l b p a th d i giti zing 5 m h z t o ne 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-003 frequency (mhz) amp l itude (dbfs ) f i gure 6. ad 9863 rx p a th sing le - t on e fft of rx ch anne l b p a th d i giti zing 2 4 mh z t o ne 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-004 frequency (mhz) amp l itude (dbfs ) f i g u re 7. a d 98 63 r x p a t h d u al- t on e f f t of r x ch anne l a p a t h d i giti zing 1 m h z a n d 2 m h z t o nes 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-005 frequency (mhz) amp l itude (dbfs ) f i g u re 8. a d 98 63 r x p a t h d u al- t on e f f t of r x ch anne l a p a t h d i giti zing 5 m h z a n d 8 m h z t o nes 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-006 frequency (mhz) amp l itude (dbfs ) f i g u re 9. a d 98 63 r x p a t h d u al- t on e f f t of r x ch anne l a p a t h d i giti zing 2 0 mh z and 25 m h z t o nes 4 .com u datasheet
AD9863 rev. a | page 11 of 40 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-007 frequency (mhz) amp l itude (dbfs ) f i g u re 10. a d 9 8 6 3 r x p a t h s i ng le - t on e fft of r x chan ne l b p a t h d i giti zing 7 6 mh z t o ne 74 65 68 71 62 0 5 10 15 20 25 03604-0-008 input frequency (mhz) s nr (dbc ) normal power @ 50msps low power @ 25msps ultralow power @ 16msps f i g u re 11. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e snr p e r f o r man c e v s . input f r equ e nc y 80 55 60 65 70 75 50 0 5 10 15 20 25 03604-0-009 input frequency (mhz) s f dr (dbc ) normal power @ 50msps low power @ 25msps ultralow power @ 16msps f i g u re 12. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e sfdr p e r f o r man c e v s . input f r equ e nc y 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-010 frequency (mhz) amp l itude (dbfs ) f i gure 13. ad9 8 6 3 rx p a th d u a l - t one fft of rx ch anne l a p a th d i giti zing 7 0 mh z and 72 m h z t o nes 74 65 68 71 62 12.0 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 0 5 10 15 20 25 03604-0-011 input frequency (mhz) s i nad (dbc ) enob ( b it s) normal power @ 50msps low power @ 25msps ultralow power @ 16msps f i g u re 14. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e sina d p e r f or m a nce v s . input f r equen c y ?50 ?55 ?60 ?65 ?70 ?75 ?80 0 5 10 15 20 25 03604-0-012 input frequency (mhz) thd (dbc ) normal power @ 50msps low power @ 25msps ultralow power @ 16msps f i g u re 15. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e thd p e r f o r man c e v s . input f r equ e nc y 4 .com u datasheet
AD9863 r e v. a| pa g e 12 of 4 0 80 10 20 30 40 50 60 70 0 0 ? 5 ? 10 ? 1 5 ? 20 ?25 ? 30 ? 3 5 ? 40 ?45 ? 50 03604-0-013 input amplitude (dbfs) s nr (dbc ) snr f i g u re 16. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e snr p e r f orman c e v s . input a m plitude 74 64 66 68 70 72 62 3.6 3.3 3.0 2.7 03604-0-014 input amplitude (dbfs) s nr (dbc ) ave ? 4 0 c ave +25 c ave +85 c f i g u re 17. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e snr p e r f o r man c e v s . a d c_a v dd and t e m p er ature ?70.0 ?75.0 ?74.5 ?74.0 ?73.5 ?73.0 ?72.5 ?72.0 ?71.5 ?71.0 ?70.5 2.7 3.0 3.3 3.6 03604-0-015 input amplitude (dbfs) thd (dbc ) ave ?40 c ave +25 c ave +85 c f i gure 18. a d 9 8 6 3 r x p a th s i ng le - t on e th d p e r f or m a nce v s . a d c_a v dd and t e mpe r at u r e 90 20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 30 40 50 60 70 80 0 ? 5 ? 10 ? 1 5 ? 20 ?25 ? 30 ?35 ? 40 03604-0-016 input amplitude (dbfs) s f dr (dbfs ) thd (dbfs ) thd sfdr f i g u re 19. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e thd and sf dr p e r f ormanc e vs . input a m plitud e enob ( b it s) 74 62 12.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 10.0 65 68 71 2.7 3.0 3.3 3.6 03604-0-017 input frequency (mhz) s i nad (dbc ) ave ?40 c ave +25 c ave +85 c f i g u re 20. a d 9 8 6 3 r x p a t h at 50 m s ps , 1 0 m h z input t o n e sinad p e r f or mance vs. adc_a v dd and t e mp e r atu r e 78 70 71 72 73 74 75 76 77 2.7 3.0 3.3 3.6 03604-0-018 input amplitude (dbfs) s f dr (dbc ) ave ?40 c ave +25 c ave +85 c f i gure 21. a d 9 8 6 3 r x p a th s i ng le - t on e sfdr p e r f o r m a nce v s . a d c_a v dd and t e mpe r at u r e 4 .com u datasheet
AD9863 rev. a | page 13 of 40 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-019 frequency (mhz) amp l itude (dbc ) f i gure 22. ad9 8 6 3 t x p a th 1 mh z s i ng le - t on e o u tput fft of t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 3 3 ? d i f f e r e nt ia l l o ad s f dr (dbc ) ?50 ? 100 50 60 70 80 90 100 ?90 ?80 ?70 ?60 0 5 10 15 20 25 03604-0-020 output frequency (mhz) thd (dbc ) sfdr thd f i gure 23. ad9 8 6 3 t x p a th t h d / sfdr v s . o u tput f r equen c y of t x ch ann e l a, wit h 20 ma f u l l -s c a l e o u t p ut in to 6 0 ? d i f f e r e nt ia l l o ad ?50 ? 100 ?90 ?80 ?70 ?60 0 5 10 15 20 25 03604-0-021 output frequency (mhz) thd (dbc ) 20ma, 33 ? 20ma, 60 ? 2ma, 600 ? f i gure 24. ad9 8 6 3 t x p a th t h d v s . o u tput f r equ e nc y of t x chann e l a 0 ?1 0 ?2 0 ?3 0 40 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 0 5 10 15 20 25 03604-0-022 frequency (mhz) amp l itude (dbc ) f i gure 25. ad9 8 6 3 t x p a th 5 mh z s i ng le - t on e o u tput fft of t x ch ann e l a wit h 20 ma f u l l -s c a l e o u t p ut in to 3 3 ? d i f f e r e nt ia l l o ad 74 64 66 68 70 72 62 0 5 10 15 20 snr sinad 25 03604-0-023 output frequency (mhz) s nr/s i nad (dbc ) f i gure 2 6 . ad98 63 t x p a th sinad/ snr vs . o u tput f r equenc y o f t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 6 0 ? d i f f e r e nt ia l l o ad ?50 ? 100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 0 5 10 15 20 25 03604-0-024 output frequency (mhz) imd (dbc ) 20ma, 60 ? 20ma, 33 ? 2ma, 600 ? f i gur e 2 7 . ad98 63 t x p a th d u al - t one (0 .5 mhz spac ing) imd vs . ou t p u t f r e q ue n c y 4 .com u datasheet
AD9863 r e v. a| pa g e 14 of 4 0 f i gur e 28 t o f i g u r e 33 us e the s a m e in p u t da ta t o th e tx p a t h , a 64-ca r r i er o f d m sig n al o v er a 20 mh z ban d wid t h, cen t er ed a t 20 mh z. the t w o cen t er ca r r i ers a r e r e mo v e d f r o m t h e s i g n al t o obs e r v e t h e in-b and i n ter m o d u l a t io n dis t o r t i o n (imd) f r o m t h e d a c o u t p ut . ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 7.5 12.5 17.5 22.5 27.5 32.5 03604-0-025 frequency (mhz) amp l itude (dbc ) f i gure 28. a d 9 8 6 3 t x p a th fft , 6 4 - c ar rie r ( t w o center ca rri ers r e m o ved) ofdm sign al o v e r 20 m h z bandwidth , centered at 2 0 m h z, with 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 03604-0-026 frequency (mhz) amp l itude (dbc ) f i gure 29. AD9863 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 28 ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 0 1 02 03 04 0 5 06 07 08 0 03604-0-027 frequency (mhz) amp l itude (dbc ) f i gur e 3 0 . ad98 63 t x p a th fft o f ofdm si gn a l i n f i gu r e 2 8 wi th 1x int e rpol at i o n ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 18.75 19.25 19.75 20.25 20.75 21.25 03604-0-028 frequency (mhz) amp l itude (dbc ) f i g u re 31. a d 9 8 6 3 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 28 ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 03604-0-029 frequency (mhz) amp l itude (dbc ) f i gure 32. AD9863 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 28 ?2 0 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 0 1 02 03 04 0 5 06 07 08 0 03604-0-030 frequency (mhz) amp l itude (dbc ) f i gure 33. AD9863 t x p a th fft of ofd m sign al in f i g u re 28 wit h 2x i n terpol at i o n 4 .com u datasheet
AD9863 rev. a | page 15 of 40 f i gur e 34 t o f i g u r e 39 us e the s a m e in p u t da ta t o th e tx p a t h , a 256-ca r r ier ofd m sig n al o v er a 1.75 mh z ban d wid t h, cen t ered a t 7 m h z. the fo ur cen t er ca r r i ers a r e r e mo v e d f r o m t h e s i g n al t o obs e r v e t h e in-b and in ter m o d u l a t io n dis t o r t i o n (imd) f r o m t h e d a c o u t p u t. ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 03604-0-031 frequency (mhz) amp l itude (dbc ) f i gure 34. a d 9 8 6 3 t x p a th fft , 2 5 6 - c arr i e r (f our center carr ie rs r e m o ved) ofdm sign al o v e r 1.75 m h z b a nd wid t h, c e ntered at 7 m h z, with 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 6.06 6.08 6.10 6.12 6.14 6.16 6.18 03604-0-032 frequency (mhz) amp l itude (dbc ) f i gure 35. AD9863 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 34 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 0 5 10 15 20 25 03604-0-033 frequency (mhz) amp l itude (dbc ) f i gur e 3 6 . ad98 63 t x p a th fft of ofd m sig n al in f i g u r e 34, with 1 i n te rp olat ion ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 6.97 6.98 6.99 7.00 7.01 7.02 7.03 03604-0-034 frequency (mhz) amp l itude (dbc ) f i g u re 37. a d 9 8 6 3 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 34 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 7.81 7.83 7.85 7.87 7.89 7.91 7.93 03604-0-035 frequency (mhz) amp l itude (dbc ) f i g u re 38. a d 9 8 6 3 t x p a t h fft , u p pe r - band im d pr oduc t s of ofdm sign al in f i g u r e 34 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 ?130 0 5 10 15 20 25 03604-0-036 frequency (mhz) amp l itude (dbc ) f i gur e 3 9 . ad98 63 t x p a th fft of ofd m sig n al in f i g u r e 34, with 2 i n te rp olat ion 4 .com u datasheet
AD9863 r e v. a| pa g e 16 of 4 0 f i gur e 40 t o f i g u r e 45 us e the s a m e in p u t da ta t o th e tx p a t h , a 256-ca r r ier ofd m sig n al o v er a 23 mh z b a nd wid t h, cen t er ed a t 2 3 m h z. the fo ur cen t er ca r r i ers a r e r e mo v e d f r o m t h e s i g n al t o obs e r v e t h e in-b and i n ter m o d u l a t io n dis t o r t i o n (imd) f r o m t h e d a c o u t p u t. ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 9 1 41 92 4 3 4 29 03604-0-037 frequency (mhz) amp l itude (dbc ) f i gure 40. a d 9 8 6 3 t x p a th fft , 2 5 6 - c arr i e r (f our center carr ie rs r e m o ved) ofdm sign al o v e r 23 m h z bandwidt h , centered at 7 m h z, w i th 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 12.1 12.3 12.5 03604-0-038 frequency (mhz) amp l itude (dbc ) f i gure 41. AD9863 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 40 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 0 1 02 03 04 05 0 6 07 08 09 0 03604-0-039 frequency (mhz) amp l itude (dbc ) f i gur e 4 2 . ad98 63 t x p a th fft of ofd m sig n al in f i g u r e 40, with 1 i n te rp olat ion ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 6.97 6.98 6.99 7.00 7.01 7.02 7.03 03604-0-040 frequency (mhz) amp l itude (dbc ) f i g u re 43. a d 9 8 6 3 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 40 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 33.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 35.1 35.3 35.5 03604-0-041 frequency (mhz) amp l itude (dbc ) f i g u re 44. a d 9 8 6 3 t x p a t h fft , u p pe r - band im d pr oduc t s of ofdm sign al in f i g u r e 40 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?120 0 1 02 0 3 04 0 5 06 07 0 8 09 0 03604-0-042 frequency (mhz) amp l itude (dbc ) f i gur e 4 5 . ad98 63 t x p a th fft of ofd m sig n al in f i g u r e 40, with 2 i n te rp olat ion 4 .com u datasheet
AD9863 rev. a | page 17 of 40 terminology input b a n d w i d t h t h e a n al og in p u t f r eq ue n c y a t wh i c h t h e s p ect r al po w e r o f th e f u ndam e n t a l f r e q uen c y (as det e r m ine d b y t h e f f t a n a l y s is) is re d u c e d b y 3 d b . ap e r t u r e d e l a y the de l a y b e t w e e n t h e 50 % p o i n t o f t h e r i sin g e d g e o f t h e clki n1 sig n a l a nd t h e i n st an t a t w h ich t h e a n a l og in p u t is ac t u a l ly s a m p le d . ap e r t u r e un c e r t a i n t y ( j i t t e r ) the s a m p le -t o-s a m p le va r i a t io n in a p er t u r e dela y . cr o s s t al k c o upl i ng on to one ch a n nel b e i n g dr i v e n b y a ? 0 . 5 d b f s signa l w h en t h e ad jacen t in t e rfe r in g ch a n n e l is dr i v en b y a fu ll - s c a l e s i gn a l . d i f f erent i a l a n a l o g input v o lt a g e r a ng e t h e peak - t o- peak d i ff e r en ti al v o l t a g e th a t m u s t be a p p l i e d t o t h e co n v e r t e r t o g e n e ra t e a f u ll-s c ale r e s p o n s e . p e ak di f f er en - t i al v o l t a g e is co m p u t e d b y ob s e r v in g t h e v o l t a g e o n a sin g le pi n and sub t r a c t i n g t h e volt age f r om t h e ot he r pi n , w h i c h is 180 o u t o f p h a s e . p e ak-t o-p e ak dif f er en tial is co m p u t ed b y r o ta ti n g th e i n p u t p h a s e 1 80 a n d taki n g th e peak m e a s ur e - m e n t a g a i n. th en t h e dif f e r en ce is co m p u t e d betw e e n b o t h p e ak m e as ur em en ts. d i f f erenti a l n o n l i n e a r i ty t h e devia t i o n o f a n y cod e wi d t h f r o m a n i d eal 1 l s b s t ep . eff e c t ive n u mb e r o f b i ts (en o b) the ef fe c t i v e n u m b er o f b i ts is c a lc u l a t e d f r o m t h e m e as ur e d s n r b a s e d on t h e fol l o w in g e q ua t i on: 02 . 6 db 76 . 1 ? = measured snr enob pu ls e w i d t h/d u ty cy cl e pu ls e wi d t h hig h is t h e m i ni m u m am o u n t o f t i m e t h a t a sig n a l s h o u l d b e lef t i n t h e log i c hig h st a t e t o achi e v e r a t e d p e r f o r m- a n ce ; p u ls e wi d t h lo w is t h e min i m u m t i me a sig n a l sh o u ld b e lef t in t h e l o w s t a t e , log i c lo w . f u l l - s c a l e input p o wer e x p r ess e d in dbm, f u l l -s c a le i n pu t p o w e r is com p u t e d using t h e fol l o w ing e q u a t i o n : ? ? ? ? ? ? ? ? = ? 001 . 0 log 10 2 input rms fullscale fullscale z v power ga in e r r o r ga i n er r o r is t h e dif f er en ce b e t w e e n t h e me asu r e d a nd i d e a l f u l l -s cale in pu t v o l t a g e ra n g e o f t h e ad c. ha r m on i c d i s t or t i on , s e c o n d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e s e c o n d h a rm o n i c c o m p o n e n t , r e p o rt e d i n d b c . ha r m on i c d i s t or t i on , t h i r d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e t h ir d ha r m o n ic co m p on e n t, r e p o r t e d in db c. inte g r a l n o n l i n e a r i t y the de v i a t ion o f t h e t r a n sfer f u n c t i on f r o m a r e fer e n c e line m e a s ur e d i n f r ac t i o n s o f a n ls b usin g a b est st ra ig h t l i n e det e r m i n e d b y a le ast s q ua r e c u r v e f i t. minim u m c o n v ersi o n r a t e th e en co de ra t e a t w h ich t h e s n r o f t h e lo w e s t a n al og sig n al f r e q uen c y dr o p s b y n o m o r e t h a n 3 db be lo w t h e g u ar an te e d l i m i t . ma x i mu m c o nve r si on r a te the e n co d e ra te a t w h ich p a ramet r ic t e st i n g is p e r f o r m e d . ou t p u t p r o p aga t io n de la y th e dela y b e tw e e n a di f f er en t i a l cr ossi n g o f clk+ a n d c l k ? a n d th e t i m e wh e n a l l o u t p u t d a ta b i t s a r e w i th i n valid l o g i c le v e l s . p o wer s u pply rej e c t i o n r a ti o the ra t i o o f a cha n g e i n i n p u t o f fs et v o l t a g e t o a cha n g e i n p o we r su p p ly v o l t age. si g n a l - t o - n o i s e a n d d i s t or t i on ( s i n a d ) the ra t i o o f t h e r m s sig n al a m pl i t u d e (s e t 1 db b e lo w f u l l s c ale) to t h e r m s v a lu e of t h e su m of a l l ot he r s p e c t r a l c o m p o n e n t s , in cl ud in g ha r m o n ics, b u t excl udin g dc. s i g n a l -t o-n o is e r a ti o (w itho u t h a rmo n i c s) the ra t i o o f t h e r m s sig n al a m pl i t u d e (s e t a t 1 db b e lo w f u l l s c ale) t o t h e r m s val u e o f t h e s u m o f al l o t h e r sp e c t r al co m p on e n ts, ex cl uding t h e f i rst f i ve ha r m o n ics a nd dc. s p uri o us-f r e e d y na mi c r a n g e (s fd r) the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f th e p e a k s p ur ious s p ec tral co m p o n en t. th e p e ak s p ur io us co m p o n en t ma y o r m a y n o t be a h a r m o n i c . i t a l so m a y be r e p o r t ed in db c (f o r exa m p l e , deg r ades as sig n a l lev e l is lo w e r e d) o r dbfs (f o r exa m p l e , al wa ys r e la t e d bac k t o co n v er t e r f u l l s c ale). s f d r do es n o t in cl ude ha r m o n ic d i stor t i on c o m p one n t s . w o rst o t h e r s p ur the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e w o rst sp ur io us co m p on e n t (excl u ding t h e s e cond an d t h ir d ha r m o n ics) r e p o r t e d in db c. 4 .com u datasheet
AD9863 r e v. a| pa g e 18 of 4 0 theory of operation system block the AD9863 is targeted to cove r the mixed-sig n al front end nee d s of multip le wirel e ss communications sys t ems. i t features a receiv e pat h t h at co nsis ts of d u al 12-b i t rece iv e adcs an d a trans m i t pat h t h at co nsis ts of dual 12-b i t tr ans m it dacs (txdac). the AD9863 integr ates additio n al fu nctio n al ity typically requir ed in mos t syste m s, such as po wer scal abil ity, tx gai n con t rol, an d clock multiplication c i rcuitry. the AD9863 minimizes bo th size and po wer consumption to add r ess th e n e ed s of a range of applications from the low power portable market to the high pe r f o r manc e bas e st atio n m a r k e t . the part is prov ide d i n a 64 -lead lead frame chi p scale pac kag e (lfcsp) th at has a footprint of on ly 9 m m 9 m m . power co nsumpt io n c a n be o p t i m i z e d to suit t h e par t i c ular applic atio n bey o nd just a sp eed gr a d e o p t i o n by i n co r p o r ating po w e r - do w n controls, low power adc mode s, txda c powe r scaling , a nd a half-duplex mode, whic h au tomatically dis a bl es the u n us ed dig i tal p a t h . the AD9863 us es two 12-bit bu ses to transfer rx path data and tx pat h data. these t w o buse s support 24-bit parallel data transfers or 12-bit interleaved data transfers. the bus is configurabl e t h rough eit h er ext e rn al mod e p i ns or in ternal registers se tting s. the regis t er s allow man y m o re option s for configuri n g the ent i re de vice . the fol l o w ing se ct io ns discu ss t h e var i o u s bloc ks of t h e ad 986 3: rx p a t h bl o c k, tx p a t h bl o c k, dig i t a l bl o c k, p r o g r a mmabl e reg i st ers, and c l o c k dis t r i b u t i o n b l o c k. rx path bl ock rx path g e neral descri ption the AD9863 rx p a th co n s ists o f tw o 12-b i t, 50 ms ps a n alog- t o -dig i t al co n v e r t e rs (ad c s). th e d u al ad c p a t h s s h a r e t h e s a m e clo c k i ng and r e fer e n c e circ ui t r y to p r o v id e o p t i ma l ma t c hin g c h a r ac t e r i s t ics. e a ch o f th e ad cs con s is ts o f a 9-stag e dif f er en t i a l p i p e line d s w i t ch e d c a p a ci to r a r chi t e c t u r e wi t h o u t p u t er r o r co rr ectio n logic. the p i p e l i n e d ar chi t e c t u r e p e r m i t s t h e f i rs t s t ag e t o o p era t e on a ne w i n p u t s a m p le , w h i l e t h e r e ma ini n g s t a g es o p era t e on p r ecedin g s a m p les. sa m p lin g o c c u rs o n t h e fal l i n g edg e o f t h e in p u t clo c k. e a ch s t a g e o f t h e p i p e l i ne , excl uding t h e last, co n s ists o f a lo w r e s o l u t i o n f l a s h a d c an d a resid u a l m u l t i p li er t o dr i v e t h e n e x t s t a g e o f t h e p i p e l i ne . the r e sid u al m u l t i p lier u s e s t h e f l a s h a d c output to c o n t rol a s w i t c h e d c a p a c i tor d i gi tal-t o - a n a log co n v e r t e r (d a c ) o f th e sa m e r e so l u ti o n . th e d a c o u t p u t is su b t rac t e d f r o m th e s t a g e s in p u t sig n al , an d t h e r e sid u a l is am pl if ie d (m u l t i plie d) t o dr i v e t h e next p i p e li n e s t a g e. th e r e si d u al m u l t i p lier st a g e is als o cal l e d a m u l t i p l y in g d a c (md a c). on e b i t o f r e d u ndan c y is us ed in each s t a g e t o facili t a te dig i tal co r r e c tio n o f f l as h er r o rs. th e las t s t a g e sim p l y co n s ists o f a f l ash ad c. the dif f er en t i al in p u t s t a g e is dc s e lf- b ias e d an d al lo ws dif f er en t i a l o r sin g le-e nde d in pu ts. t h e o u t p u t - s t a g i n g b l o c k a l i g n s th e d a ta , c a rri e s o u t th e e r r o r c o r r e c t i o n , a n d pa s s e s th e da ta t o th e o u t p u t b u f f e r s. the l a t e n c y o f t h e rx p a t h is ab o u t 5 clo c k c y cles. r x path an alo g inp u t e qui v a lent c i rc uit the rx p a t h a n alog in p u ts o f th e AD9863 in c o r p o r a t e a n o vel s t r u ct ur e th a t m e r g e s th e fun c tio n o f th e i n p u t sa m p le - a n d - h o ld a m plif iers (s h a s) a n d t h e f i rst p i p e li n e r e si d u e a m plif iers i n t o a sin g le , com p ac t swi t ch ed ca p a c i t o r cir c ui t. b y e l imina t in g on e a m plif ier i n t h e p i p e li n e , t h is st r u c t ur e achi e v es co n s idera b le n o is e and p o w e r s a v i n g s o v er a co n v e n t i o n al im plem e n t a t i o n t h a t us es s e p a ra t e a m pl if iers. f i gur e 46 il l u s t ra t e s t h e e q ui val e n t a n alog in p u ts o f th e ad986 3 (a swi t ch e d ca p a ci t o r in p u t). b r in g i ng clk t o log i c hig h o p en s s w i t ch s3 an d c l os es s w i t ch s1 and s w i t c h s2; this is th e s a m p le m o de o f t h e i n pu t cir c ui t. th e i n p u t s o ur ce co nn e c te d t o vi n+ a nd vi n? m u st cha r ge ca p a ci tor c h d u ri n g th i s ti m e . b r i n gin g clk t o a log i c l o w o p ens s w i t ch s2, an d t h e n s w i t ch s1 op en s, fol l o w e d b y t h e closin g o f s w i t ch s3. this p u ts t h e in pu t cir c u i t in t o h o ld m o de . 03604-0-073 v in+ r in v cm c in c h s1 s3 s2 c h c in r in v in? + ? f i g u re 46. d i f f e r e nt ia l input a r ch itec t u r e the s t r u c t ur e o f t h e in p u t sh a places cer t a i n r e q u ir e m en ts o n t h e in p u t dr i v e s o ur ce . th e dif f er en t i al i n p u t r e sis t o r s a r e typ i c a l l y 2 k? e a ch. the com b i n a t io n o f t h e pi n ca p a c i t a n c e , c in , a n d th e h o ld ca pa ci ta n c e , c h , is typ i cal l y les s t h a n 5 pf . th e in p u t s o ur ce m u s t be ab le t o c h a r g e o r dis c ha rg e this c a p a ci - t a nc e to 1 2 - bit a c c u r a c y i n one - h a l f of a cl o c k c y cl e. w h e n t h e s h a g o es i n t o s a m p le m o de , t h e in pu t s o ur ce m u s t cha r g e o r dis c ha rge c a p a ci to r c h f r om t h e vo lt age a l re a d y store d on it to t h e ne w v o l t a g e . i n t h e w o rst cas e , a f u l l -s cale vol t a g e s t ep o n t h e in p u t s o ur c e m u s t p r o v ide t h e cha r g i ng c u r r en t t h r o ug h t h e r on o f s w i t ch s 1 (typ ical l y 100 ?) t o a s e t t led vol t a g e wi t h in o n e- half o f t h e ad c s a m p le p e r i o d . this si t u a t io n co r r es p o nds to dr i v in g a lo w in p u t i m p e dance. on t h e o t h e r ha nd , w h e n t h e s o ur ce v o l t a g e e q uals t h e v a l u e p r e v io us l y st o r e d o n c h , t h e h o ld c a p a ci t o r r e q u ir es n o in put c u r r en t an d t h e e q ui v a len t in p u t im p e dan c e is ext r eme l y hig h . 4 .com u datasheet
AD9863 rev. a | page 19 of 40 rx path a ppli c ation s e ction a d din g s e r i es r e sis t a n c e betw een t h e o u t p u t o f th e s i g n al s o ur c e a nd t h e vi n p i n s r e d u ces t h e dr i v e r e q u ir e m en ts place d o n t h e sig n a l s o ur ce . f i gur e 47 sh o w s t h is co nf igura t ion. 03604-0-074 r series r series vin+ c shunt AD9863 vin ? f i gure 47. t y pic a l i n put t h e ba n d w id th o f th e pa r t i c ula r a p p l i c a t i o n li m i t s th e s i z e o f t h is r e sist o r . f o r a p p l ica t io n s wi t h sig n a l ba n d w id t h s less th a n 10 mh z, t h e user ma y in s e r t s e r i es in p u t r e sis t o r s a n d a s h un t ca p a ci t o r t o p r o d uce a lo w-p a s s f i l t e r f o r th e i n p u t signal . i n addi t i o n , addin g a sh un t ca p a ci t a n c e b e tw e e n t h e vin p i n s ca n lo w e r t h e a c l o ad im p e da n c e . th e val u e o f t h is ca p a ci t a n c e dep e n d s o n t h e s o ur ce r e sis t a n ce a n d th e r e q u i r e d s i g n a l b a ndw i d t h . t h e r x i n put p i ns are s e l f - b i a s e d to prov i d e t h i s m i d s upp l y , co mm on- m o d e b i a s vol t a g e, s o i t is r e co m m e nde d to ac co u p l e th e s i g n al t o t h e in p u ts usin g dc b l o c kin g ca p a c i t o rs. i n sys t em s tha t m u s t us e dc co u p lin g , us e a n o p a m p t o co m p l y wi th t h e in p u t r e q u ir emen ts o f t h e ad9 863. the in p u ts accep t a sig n al wi t h a 2 v p-p dif f er en t i al i n p u t sw in g ce n t er e d ab o u t on e- hal f o f t h e su p p l y v o l t a g e (a vdd/2) . i f t h e dc b i as is s u p p lie d ext e r - na l l y , t h e i n ter n a l in p u t b i a s circ ui t sh o u l d b e p o w e r e d do w n b y wr i t in g t o r e g i sters rx_a dc b i as [reg is ter 0x03, b i t 6] a nd rx_b dc b i as [ r eg is t e r 0x04, b i t 7]. the ad cs in t h e AD9863 a r e desig n e d t o s a m p le dif f er en t i al in p u t sig n als. th e dif f er en t i al i n p u t p r o v i d es i m p r o v e d n o is e imm u ni ty an d b e t t er thd and s f dr p e r f o r ma n c e fo r t h e rx p a th. i n sys t e m s tha t us e sin g le-ende d sig n als, t h es e in p u ts ca n b e dig i t i ze d , b u t i t is r e co m m e nde d t h a t a sin g l e -e n d e d - t o - dif f er en t i a l con v ersio n b e p e r f o r m e d. a sing le- e nde d - to - dif f er en t i a l con v ersio n can b e p e r f o r m e d b y usin g a t r a n sfo r m e r co u p lin g cir c u i t (typ ical l y f o r sig n als a b o v e 10 mh z) o r b y usin g a n o p er a t io nal a m p l if ier , suc h as t h e ad8 138 (typ ical l y fo r sig n als be lo w 10 mh z). adc volta g e references the AD9863 12 -b i t ad cs us e in t e r n al r e f e r e n c es tha t a r e desig n e d t o p r o v ide fo r a 2 v p-p dif f er en t i al i n p u t ra n g e . th e i n te r n a l b a nd g a p re f e re nc e ge ne r a te s a s t abl e 1 v re f e re nc e le vel and is de c o u p le d t h r o ug h t h e vref p i n. ref t an d ref b a r e t h e dif f er en t i al r e fer e n c e s g e n e ra t e d b a s e d o n t h e v o l t a g e l e vel of v r e f . fi g u re 4 8 s h o w s t h e prop e r d e c o upl i ng of t h e re fe r e nc e pi ns v r e f , r e f t , a n d r e f b w h e n u s i n g t h e i n te r n a l re f e re nc e . d e c o up l i ng c a p a c i tor s shou l d b e p l a c e d a s cl o s e to t h e re f e re nc e pi ns a s p o ss i b l e . e x t e r n al r e fer e n c es reft an d r e fb a r e cen t er e d a t a v d d /2 w i th a di f f e r e n tial v o l t a g e e q ual t o th e v o l t a g e a t v r ef (b y defa u l t 1 v w h e n usin g t h e in te r n a l r e fer e n c e), a l lo w i n g a p e a k - t o -p e a k dif f er en t i al v o l t a g e s w i n g o f 2 vref . f o r exa m ple , t h e defa u l t 1 v vref r e f e r e n c e accep t s a 2 v p-p dif f er en tial in p u t swi n g, and t h e o f fs et v o l t a g e sho u ld b e reft = a v d d /2 + 0.5 v refb = a v d d /2 ? 0.5 v 03604-0-075 0.1 f 0.1 f 10 f 0.1 f 0.1 f vref AD9863 0.5v to adcs reft refb 10 f f i g u re 48. t y pic a l r x p a t h d ecoupl i ng an ext e r n al r e fer e n c e ma y b e us e d fo r sys t em s t h a t r e q u ir e a dif f er en t i n p u t v o l t a g e ra n g e , hig h ac c u rac y ga in ma t c hin g b e tw e e n m u l t i p le de vices, o r i m p r o v em e n ts in tem p er a t ur e dr if t a nd n o is e cha r ac t e r i s t ics. w h en a n ext e r n al r e fer e n c e is desir e d , t h e in ter n a l rx b a nd ga p r e fer e n c e m u st b e p o w e r e d do w n usin g t h e vref r e g i s t er [reg ister 0x05, bi t 4], wi t h t h e ext e r n al r e fer e n c e dr ivi n g t h e v o l t a g e l e ve l o n t h e vref p i n. th e ext e r - nal v o l t a g e l e v e l s h o u l d b e on e- half o f t h e desire d p e ak- t o-p e a k dif f er en t i al v o l t a g e s w ing. the r e s u l t is t h a t t h e dif f er en t i al v o l t a g e r e fer e n c es a r e dr i v en t o ne w v o l t a g es: reft = a v d d /2 + v ref /2 v refb = a v d d /2 ? v ref /2 v i f an e x te r n a l re f e re nc e i s u s e d , it i s re c o m m e n d e d not to e x c e e d a dif f er en t i al o f fs et v o l t a g e g r e a ter t h a n 1 v fo r t h e r e fer e n c e . c l ock i n p u t a n d c o ns id er at ions t y p i cal hig h s p eed ad cs us e b o th c l o c k e d g e s t o g e n e ra t e a v a r i e t y of i n te r n a l t i m i ng s i g n a l s an d, a s a re su lt , m a y b e s e ns i- ti v e t o c l oc k d u ty c y c l e . c o mm o n l y , a 5% t o le ra n c e i s r e q u i r ed o n t h e clo c k d u t y c y c l e t o ma in t a in d y na mic p e r f o r ma n c e c h a r ac t e r i s t ics. the AD9863 con t a i n s c l o c k d u ty c y c l e s t a b il izer cir c ui tr y (d cs). t h e d c s r e t i m e s t h e in t e r n al ad c c l o c k (n o n s a m p lin g e d ge) a nd p r o v id es t h e ad c w i t h a n o m i na l 50 % d u ty c y cle . i n p u t clo c k ra t e s o f o v er 40 mh z can us e t h e d c s s o t h a t a w i de ra n g e o f in p u t clo c k d u ty c y cles ca n b e acco mm o d a t ed. c o n v ers e l y , d c s sh o u ld n o t b e us ed f o r rx s a m p ling b e lo w 40 ms ps. m a in ta inin g a 50 % d u ty c y c l e c l o c k is p a r t ic u l a r ly im p o r t a n t i n hi g h sp e e d a p pli c a t io n s w h e n p r o p er s a m p le-and- h o l d t i m e s fo r t h e co n v er t e r a r e r e q u ir e d t o ma in t a i n hig h p e r f o r ma n c e. t h e d c s can b e e n a b le d b y w r i t i n g hi gh s t o th e r x _ a /r x_b c l k d u t y r e gi s t e r b i t s [reg is t e r 0x06/reg i st er 0x07, b i t 4]. the d u ty c y cle s t a b i l i z er us es a dela y-lo cke d lo o p t o cr e a t e t h e n o n s am pli n g e d ge. a s a r e su l t , an y cha n ges t o t h e s a m p li n g f r e q uen c y r e q u ir e a p p r o x ima t e l y 2 s t o 3 s t o a l lo w t h e dll to a d j u st to t h e ne w r a t e a n d s e tt l e . h i g h sp e e d, h i g h re s o lut i on ad cs a r e s e n s i t i v e t o t h e qual i t y o f t h e clo c k in p u t. the 4 .com u datasheet
AD9863 r e v. a| pa g e 20 of 4 0 deg r a d a t io n i n s n r a t a g i ven f u l l -s ca le in p u t f r e q uen c y (f inp u t ), d u e t o a p er t u r e ji t t er (t a ), ca n b e calc u l a t e d wi t h t h e f o l l o w in g eq ua ti o n : snr deg r ada t i o n = 20 log [(?) f in t a )] i n t h e e q ua ti o n , th e rm s a p e r t u r e j i t t e r , t a , r e p r es en ts t h e r o o t - s u m-s q ua r e o f a l l ji t t er s o ur ces, which in c l udes th e c l o c k in p u t, a n a l og in p u t sig n a l , an d ad c a p er t u r e j i t t e r sp e c if ica t ion. u n ders am pli n g a p plic a t io n s a r e p a r t ic u l a r ly s e nsi t i v e t o ji t t er . t h e c l oc k i n p u t i s a d i g i tal si gnal th a t sh o u ld b e tr ea t e d a s a n a n alog si gn al wi th logi c lev e l thr e s h o l d v o l t a g es, es peci all y i n cas e s w h er e a p e r t u r e ji t t er ma y a f fe c t t h e d y namic ra n g e o f t h e AD9863. p o w e r s u p p lies f o r c l o c k dr i v ers s h o u l d b e s e p a ra t e d f r o m t h e a d c o u t p ut dr i v er s u p p lies t o a v o i d m o d u l a t i n g t h e c l oc k s i gn al wi th di gi tal n o ise . lo w j i t t e r c r ys tal - c o n t r o ll ed os cil l a t o r s mak e th e best c l o c k s o ur ces. i f the c l o c k is g e n e ra t e d f r om anot he r t y p e of s o u r c e ( b y g a t i n g , d i v i d i n g , or ot he r me t h - o d s), i t sh o u l d b e r e tim e d b y t h e o r ig inal c l o c k a t the last s t ep . pow er dis s i pa tion an d st an db y mo de the p o wer dis s i p a t io n o f t h e AD9863 rx p a th is p r o p o r tio n al t o i t s sa m p li n g ra t e . th e r x pa th po r t i o n o f th e di gi tal (d r v d d ) p o w e r diss i p a t i o n is deter m i n e d p r ima r i l y b y t h e st r e n g t h o f t h e dig i t a l dr i v ers and t h e lo ad o n e a ch o u t p u t b i t. the d i g i t a l dr i v e cu rr e n t c a n be cal c ul a t ed b y i dr v d d = v dr v d d c loa d f cl o c k n w h er e n is t h e n u m b er o f b i ts c h a n g i n g and c loa d is t h e a v er ag e lo ad o n t h e dig i tal p i n s tha t chan g e d . t h e a n al og ci r c ui tr y i s o p ti m a ll y b i a s ed so tha t ea c h s p eed g r ade p r o v i d es exce l l en t p e r f o r ma n c e w h i l e a f fo r d in g r e d u ce d p o w e r co n s u m pt io n. e a ch sp e e d g r ade dissi p a t es a b a s e li n e p o w e r a t lo w s a m p le ra t e s, which in cr e a s e s wi th c l o c k f r e - q u en c y . the b a s e li n e p o w e r dis s i p a t ion fo r ei t h e r s p e e d g r ade ca n b e r e d u ce d b y ass e r t i n g t h e ad c_lo_ p w r p i n, w h ich r e d u c e s in t e rn al a d c b i a s cu rr e n t s b y h a l f , i n so m e c a se s re su lt i n g i n d e g r a d e d p e r f or m a nc e . t o f u r t h e r r e d u ce p o w e r co n s um p t io n o f the ad c, t h e ad c_l o _pwr p i n ca n be c o m b in ed wi th a s e r i al p r og ra mma b l e r e g i s t er s e t t i n g to co nf igur e a n u l t r alo w p o wer m o de . the ul tralo w p o wer m o d e r e d u ces p o w e r co n s um p t io n b y a f o ur th of t h e nor m a l p o we r c o nsu m pt i o n . t h e u l t r a l ow p o we r mo d e ca n be us e d a t s l o w er s a m p lin g f r eq uen c ies o r if r e d u ced p e r f o r ma n c e is accep t ab le. t o c o nf igur e t h e u l t r a l o w p o w e r m o de, ass e r t t h e ad c_lo _p wr p i n d u r i n g p o w e r - u p and wr i t e t h e fol l o w in g r e g i s t er s e t t i n gs: reg i st er 0x08 (ms b ) 0000 1100 reg i st er 0x09 (ms b ) 0111 0000 reg i st er 0x0a (ms b ) 0111 0000 f i g u re 4 9 sh o w s t h e typ i ca l a n alog p o wer d i s s i p a t io n ( a d c _ a v d d = 3.3 v) f o r th e ad c vs. sam p lin g ra t e f o r the n o r m a l p o w e r , l o w p o wer , a nd u l t r a l o w p o wer m o des. ei t h er o f the ad cs in t h e ad9 863 rx p a th can be p l aced in s t and b y m o de in dep e nden t l y b y wr i t in g t o t h e a p p r o p r i a t e s p i r e gi s t e r b i t s in r e gi s t e r 3 , re gis t e r 4 , a n d r e gis t e r 5 . th e mini m u m st andb y p o w e r is achi e v e d w h en b o t h cha nnels a r e p l aced in f u l l p o w e r - do wn m o de usin g t h e a p p r o p r i a t e s p i r e gi s t e r b i t s in r e gi s t e r 3 , re gis t e r 4 , a n d r e gis t e r 5 . u n d e r thi s co ndi t i on, t h e i n ter n a l r e fer e n c es a r e p o w e r e d do wn. w h e n ei t h er o r b o t h of t h e chann e l p a t h s a r e ena b le d a f t e r a p o w e r - do wn, t h e wa ke -u p t i m e is dir e c t ly r e la te d to t h e r e cha r g i n g of t h e ref t and r e f b de co u p lin g ca p a ci to rs a nd t h e d u r a t i o n o f t h e p o we r - d o w n . t y pi c a l l y , it t a ke s a pprox i m atel y 5 ms to r e s t o r e f u l l o p era t io n wi th f u l l y dis c ha rg ed 0.1 f a n d 10 f deco u p ling ca p a ci t o rs o n ref t an d refb . 20 40 60 80 100 120 0 0 5 10 15 20 25 30 35 40 45 50 03604-0-043 rx path sampling rate (mhz) av dd curre nt (ma) ultralow power low power normal f i g u re 49. t y pic a l r x p a t h a n a l og s u p p ly cur r ent v s . s a m p le r a t e , v dd = 3. 3 v f o r no r m a l , l o w , and u l t r al o w p o wer m o des tx pa th bl ock the AD9863 tr a n smi t ( t x) p a t h in c l udes d u al in t e r p ol a t in g 12-b i t c u r r en t ou t p u t d a cs tha t ca n be op era t e d in dep e nden t l y o r ca n b e co u p l e d t o f o r m a com p lex s p ec tr u m in a n ima g e rej e c t t r ans m i t archi t e c t u re. e a ch chan nel i n clu d es two f i r f i l t ers, makin g t h e AD9863 c a p a b l e o f 1, 2, o r 4 in t e r p ola - t i o n . h i g h sp e e d i n p u t and o u tp u t da t a r a te s can b e achi e v e d w i t h i n th e li m i ta t i o n s l i s t e d i n t a b l e 9 . table 9. ad 98 63 tx path ma ximum data r a te interpolation rate 24-bit interfac e mode input data rate per channel (msps) dac sampling rate (msps) fd, hd12, clone 80 80 1 h d 2 4 1 6 0 1 6 0 fd, hd12, clone 80 160 2 h d 2 4 8 0 1 6 0 fd, hd12, clone 50 200 4 h d 2 4 5 0 2 0 0 by u s ing t h e d u a l d a c out p uts to for m a c o m p l e x s i g n a l , an ext e rn al a n alog q u ad ra t u r e m o d u la t o r , s u c h a s th e a n alog de vices ad834 9, ca n ena b le an ima g e r e jec t ion a r c h i t ec t u r e . (n o t e: t h e ad9 863 eval ua t i o n bo a r d in c l u d es a q u adra t u r e m o d u l a t o r in t h e tx p a t h tha t acco mmo da t e s t h e ad8345, ad8346, an d ad8349 f o o t p r in ts.) t o o p timize th e ima g e r e jec t io n ca p a b i li ty as we l l as lo f eed thr o ug h s u p p r es sio n in 4 .com u datasheet
AD9863 rev. a | page 21 of 40 this a r c h i t e c t u r e , th e AD9863 o f f e rs p r ogra mma b l e (via t h e s p i p o r t ), f i n e (tr i m) ga in an d o f fs et ad j u s t m e n t f o r eac h d a c. als o in c l uded in t h e AD9863 ar e a p h as e-lo ck e d lo o p (p ll) clo c k m u l t i p lier a nd a 1.2 v b a nd ga p vol t a g e r e fer e n c e. w i t h t h e p l l en a b l e d , a c l ock a p p l i e d t o t h e clk i n 2 in p u t is m u l t i p lied i n te r n a l ly and ge ne r a te s a l l ne c e ss ar y i n te r n a l sy n c hr o n iz a t io n clo c ks. e a ch 12 -b i t d a c p r o v i d es tw o c o m p l e m e n t a r y cu rr e n t o u t p u t s wh os e full - s cale cu rr e n t s c a n be d e t e rmin ed f r o m a s i n g le e x t e rn al r e s i s t o r . an ext e r n al p i n, txpwrd wn, ca n be us e d t o p o w e r do wn t h e tx p a t h w h e n no t i n u s e, o p t i m i z i ng sy ste m p o wer consu m p t ion. u s in g t h e tx p w r d w n pin d i s a b l es clo c ks and s o m e a n a l o g cir c ui tr y , s a vin g bo t h dig i ta l and a n alog p o w e r . the p o wer - do wn m o de le a v es t h e b i as es e n a b le d to faci li t a te a q u ick r e co v- er y t i m e , typ i cal l y <10 s. i n addi t i on, a s l e e p m o de is a v a i la b l e t h a t tu r n s of f t h e d a c output c u r r e n t but l e a v e s a l l ot he r cir c ui ts ac t i v e f o r a m o des t p o w e r s a vin g s. an s p i-co m p l i an t s e r i al p o r t is us ed t o p r og ra m t h e man y f e a t ur es o f th e AD9863 . n o t e th a t i n po w e r - d o w n m o d e , th e s p i po rt i s s t i l l a c t i v e . dac equ i va lent circu i ts the AD9863 tx p a th, co n s is t i ng o f d u al 12 -b i t d a cs, is s h o w n in f i gur e 50. the d a cs in t e g r a t e a hi g h p e r f o r ma n c e tx d a c c o re, a pro g r a m m a bl e g a i n c o n t ro l t h rou g h a pro g r a m m a bl e ga in am plif ier (txpga), co a r s e ga in co n t r o l, and o f fs et a d j u s t - m e n t a n d f i n e ga in co n t r o l t o co m p en s a t e f o r s y s t em m i sma t ch es. c o a r s e ga in a p plies a g r os s s c al in g t o ei t h er d a c b y 1, (1/2), o r (1/11). th e txpga p r o v ides ga in co n t r o l f r o m 0 db t o C20 db in st eps o f 0.1 db a nd is co n t r o l l ed via t h e 8-b i t txp g a s e t t ing. a f i n e g a in a d j u st m e n t o f 4% fo r e a ch cha nne l is con - tr ol led thr o ug h a 6-b i t f i n e ga in r e g i s t er . b y def a u l t, co a r s e ga in is 1, t h e txpg a is s e t t o 0 db , a nd t h e f i n e ga i n is s e t t o 0%. the tx d a c co re o f t h e ad986 3 p r o v ides d u al , dif f er en t i al , c o m p l e me n t ar y c u r r e n t output s ge ne r a te d f r om t h e 1 2 - b i t d a t a . the 12-b i t d u al d a cs s u p p o r t u p da te ra t e s u p t o 200 ms ps. the dif f er en t i al o u t p uts (i o u t+ a n d io u t C) o f e a ch d u al d a c are c o m p l e me n t ar y , me an i n g t h a t t h e y a l w a y s a d d up to t h e f u l l - s c a l e c u r r e n t output of t h e d a c , i ou t f s . o p t i m u m ac p e r f o r ma n c e is achie v e d w h en t h e dif f er en t i al c u r r en t in t e r f ace dr i v es ba lan c e d lo ads o r a tra n sf o r m e r . 03604-0-076 reference bias iout+a pga iout?a + + + + txdac offset dac iout+b pga iout?b + + + + txdac offset dac f i gure 50. t x d a c o u tput struc t ur e bl o c k d i agr a m the f i n e ga in con t r o l p r o v ides im p r o v ed b a lan c e o f q a m m o d u l a t e d sig n als, r e s u l t in g in im p r o v e d m o d u la tion acc u rac y a nd im a g e r e j e c t io n. the i n d e p e nde n t d a c a and d a c b o f fs et con t r o l adds a sm a l l dc c u r r en t t o ei t h er i o u t + o r i o ut C (n ot b o t h ). th e s e le c t ion o f w h ich iou t t h is o f fs et c u r r en t is d i r e c t e d t o wa r d is p r og ra mma b l e v i a r e g i st er s e t t i n g. of fs et co n t r o l ca n b e us e d fo r s u p p r es sio n o f a l o le aka g e sig n al tha t typ i c a l l y r e s u l t s a t th e ou t p u t o f t h e m o d u la t o r . i f t h e AD9863 is dc-co u p l ed t o an e x te r n a l mo d u l a tor , t h i s fe a t u r e c a n b e u s e d to c a nc el t h e out p ut o f fs et o n the AD9863 as w e l l as th e in p u t o f fs et o n t h e mo d u l a tor . t h e re f e re nc e c i rc u i t r y i s show n i n f i g u re 5 1 . 03604-0-077 dac a and dac b reference biases fsadj refio 0.1 fr set 4k ? current source array i outfsmax i ref 1.2v reference f i gure 51. r e ference ci r c u i tr y r e f e rri n g t o t h e tra n sf e r fun c ti o n o f th e f o llo w in g eq ua ti o n , i ou tf s m a x i s th e m a xi m u m curr e n t o u t p u t o f th e d a c wi th th e defa u l t ga in s e t t in g (0 db) and is b a s e d on a r e fer e n c e c u r r en t, i ref . i ref is s e t b y t h e in t e r n al 1. 2 v r e fer e n c e and t h e ext e r n al r set res i stor . i ou t f sm a x = 64 ( refi o/r set ) ty p i c a l l y , r set is 4 k?, w h ich s e t s i ou tf s m a x to 2 0 ma , t h e o p ti m a l d y n a mic se t t i n g f o r th e t x d a c s . i n cr easi n g r set by a f a c t or of 2 prop or t i on a l ly d e c r e a s e s i ou t f sma x b y a f a c t or of 2 . i ou tf s m a x o f eac h d a c ca n b e r e s c ale d ei t h er sim u l t an eo us l y , usin g t h e txpg a ga in r e g i st er , o r in d e p e nden t ly , usin g t h e da c a / da c b c o a r s e g a i n r e g i s t e r s . t h e t x p g a f u n c t i on prov i d e s 2 0 d b of s i m u lt a n e o u s g a i n ra n g e f o r bo th d a cs, an d i t is co n t r o lled b y wr i t in g t o t h e s p i r e g i s t er txpg a ga in fo r a p r og ra mma b l e f u l l - s c a le o u t p u t o f 10% t o 10 0% o f i outfs m a x . th e ga i n c u r v e is lin e a r in db , wi t h s t eps o f a b o u t 0. 1 db . i n t e r n all y , th e ga i n is c o n t r o l l ed b y c h a n g i n g th e ma in d a c b i as curr en ts wi th a n i n t e r n al t x pga d a c wh os e o u t p u t is h e a v il y f i l t e r ed via a n o n -c hi p r - c f i l t er t o p r o v ide co n t i n uo us ga i n tra n si ti o n s . n o t e th a t th e se t t li n g ti m e a n d ba n d w id th o f th e txpga d a c c a n be im p r o v ed b y a fac t o r o f 2 b y wr i t in g t o th e txpga fas t u p da t e r e gis t er . e a c h d a c has i n dep e n d en t co a r s e ga in c o n t r o l . c o a r s e ga in co n t r o l ca n be used t o a cco mm o d a t e dif f e r en t i ou t f s fr o m th e d u al d a cs. th e c o a r se f u l l -s cal e o u t p u t co n t r o l ca n be ad j u s t ed b y usin g th e d a c a/d a c b c o a r s e ga in r e g i s t er s t o 1/ 2 o r 1/11 o f th e nom i n a l f u l l - s c a le c u r r e n t . f i n e ga in co n t rols a n d dc o f fs et co n t r o ls ca n b e us ed t o co m p ens a te fo r misma t ch es (fo r sys t em le ve l c a l i b r a t io n), a l l o w i n g i m p r o v e d ma t c hin g ch a r ac t e r i s t ics o f t h e tw o tx 4 .com u datasheet
AD9863 rev. a| page 22 of 40 channels and aiding in suppressing lo feedthrough. this is especially useful in image rejection architectures. the 10-bit dc offset control of each dac can be used independently to pro- vide an offset of up to 12% of i outfsmax to either differential pin, thus allowing calibration of any system offset. the fine gain control with 5-bit resolution allows the i outfsmax of each dac to be varied over a 4% range, allowing compensation of any dac or system gain mismatches. fine gain control is set through the dac a/dac b fine gain registers, and the offset control of each dac is accomplished using the dac a/dac b offset registers. clock input configuration the quality of the clock and data input signals is important in achieving optimum performance. the external clock driver circuitry provides the AD9863 with a low jitter clock input that meets the min/max logic levels while providing fast edges. when a driver is used to buffer the clock input, it should be placed very close to the AD9863 clock input, thereby negating any transmission line effects such as reflections due to mismatch. programmable pll clkin2 can function either as an input data rate clock (pll enabled) or as a dac data rate clock (pll disabled). the pll clock multiplier and distribution circuitry produce the necessary internal timing to synchronize the rising edge trig- gered latches for the enabled interpolation filters and dacs. this circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), and clock distribution block, all under spi port control. the charge pump, phase detector, and vco are powered from pll_avdd, while the clock distribu- tion circuits are powered from the dvdd supply. to ensure optimum phase noise performance from the pll clock multiplier circuits, pll_avdd should originate from a clean analog supply. the speed of the vco within the pll also has an effect on phase noise. the pll locks with vco speeds as low as 32 mhz up to 350 mhz, but optimal phase noise with respect to vco speed is achieved by running it in the range of 64 mhz to 200 mhz. power dissipation the AD9863 tx path power is derived from three voltage supplies: avdd, dvdd, and drvdd. idrvdd and idvdd are very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. iavdd has the same type of sensitivity to data, interpolation rate, and the modulator function, but to a much lesser degree (<10%). sleep/power-down modes the AD9863 provides multiple methods for programming power saving modes. the externally controlled txpwrdwn or spi programmed sleep mode and the full power-down mode are the main options. txpwrdwn is used to disable all clocks and much of the analog circuitry in the tx path when asserted. in this mode, the biases remain active, therefore reducing the time required for re-enabling the tx path. the time of recovery from power-down for this mode is typically less than 10 s. sleep mode, when activated, turns off the dac output currents, but the rest of the chip remains functioning. when coming out of sleep mode, the AD9863 immediately returns to full operation. a full power-down mode can be enabled through the spi register, which turns off all tx path related analog and digital circuitry in the AD9863. when returning from full power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. interpolation stage interpolation filters are available for use in the AD9863 transmit path, providing 1 (bypassed), 2, or 4 interpolation. the interpolation filters effectively increase the tx data rate while suppressing the original images. the interpolation filters digitally shift the worst-case image further away from the desired signal, thus reducing the requirements on the analog output reconstruction filter. there are two 2 interpolation filters available in the tx path. an interpolation rate of 4 is achieved using both interpolation filters; an interpolation rate of 2 is achieved by enabling only the first 2 interpolation filter. the first interpolation filter provides 2 interpolation using a 39-tap filter. it suppresses out-of-band signals by 60 db or more and has a flat pass-band response (less than 0.1 db ripple) extending to 38% of the input tx data rate (19% of the dac update rate, f dac ). the maximum input data rate is 80 msps per channel when using 2 interpolation. the second interpolation filter provides an additional 2 interpola- tion for an overall 4 interpolation. the second filter is a 15-tap filter, which suppresses out-of-band signals by 60 db or more. the flat pass-band response (less than 0.1 db attenuation) is 38% of the tx input data rate (9.5% of f dac ). the maximum input data rate per channel is 50 msps per channel when using 4 interpolation. latch/demultiplexer data for the dual-channel tx path can be latched in parallel through two ports in half-duplex operations (hd24 mode) or through a single port by interleaving the data (fd, hd12, and clone modes). see the flexible i/o interface options section in the digital block description that follows and the clock distribution block section for further descriptions of each mode. 4 .com u datasheet
AD9863 rev. a | page 23 of 40 digi tal block flexible i/o interface optio n s th e AD9863 di g i tal b l o c k al lo ws th e device t o be c o n f igu r ed in va r i o u s t i mi n g a n d o p er a t io n m o des. th e f o llo win g s e c - ti o n s d i scu s s th e f l e x i b le i/ o i n t e rfa c e s , th e c l oc k d i s t ri b u ti o n b l o c k, a n d t h e p r ogra mmin g o f t h e de vice t h r o ug h m o de p i n s or spi re g i ster s . the AD9863 can acco mm o d a t e va r i o u s da ta in ter f ace tra n sf er o p tio n s (f lexi b l e i/o). th e AD9863 us es tw o 1 2 -b i t b u s e s, an u p p e r b u s (u12 ) a n d a lo w e r b u s (l12), t o tra n sf er th e d u al- cha nnel 12- b i t ad c da t a and d u a l -cha n n el 12 -b i t d a c da t a b y m e a n s o f in t e r l e a v e d da ta , p a ralle l da ta , o r a mi x o f bo th . t a b l e 10 s h o w s t h e dif f er en t i/ o co nf igu r a t io n s o f t h e mo des de p e n d in g o n half-d u p lex o r f u l l -d u p lex o p era t ion. t a b l e 11 a nd t a b l e 12 summa r i ze t h e p i n co nf igur a t ion s vs. t h e m o de s. table 10. flexi b le data interface modes mode name tx only mode ( h alf- duplex) rx o n ly mo de ( h alf- duplex) concurrent tx + rx mode (full- duplex) general notes hd24 u[0:11] digital back end AD9863 tx_a data 03604-0-078 l[0:11] tx_b data iface1 tx/rx iface2 output clock iface3 output clock l[0:11] digital back end AD9863 rx_a data 03604-0-082 rx_b data u[0:11] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 1 ad c samp le rate two 1 2 -bit pa ralle l rx data buses tx data rate = 1 ad c samp le rate two 1 2 -bit pa ral l e l tx da ta buses hd12 u[0:11] digital back end AD9863 tx_a/b data 03604-0-079 l[11] txsync iface1 tx/rx iface2 output clock iface3 output clock u[11] digital back end AD9863 rxsync 03604-0-083 rx_a/b data l[0:11] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 2 ad c samp le rate one 12-bit inte rle a ved rx data bus tx data rate = 2 ad c samp le rate one 12-bit inte rle a ved tx data bus fd u[0:11] digital back end AD9863 tx_a/b data 03604-0-080 l[0:11] iface1 txsync iface2 output clock iface3 output clock u[0:11] digital back end AD9863 03604-0-084 rx_a/b data l[0:11] iface1 iface2 output clock iface3 output clock u[0:11] digital back end AD9863 tx_a/b data 03604-0-086 rx_a/b data l[0:11] iface1 txsync iface2 output clock iface3 output clock rx data rate = 2 ad c samp le rate one 12-bit inte rle a ved rx data bus tx data rate = 2 ad c samp le rate one 12-bit inte rle a ved tx data bus clone u[0:11] digital back end AD9863 tx_a/b data 03604-0-081 txsync l[11] iface1 tx/rx iface2 output clock iface3 output clock u[0:11] digital back end AD9863 rx_a data 03604-0-085 rx_b data l[0:11] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 1 ad c samp le rate two 1 2 -bit pa ralle l rx data buses tx data rate = 2 ad c samp le rate one 12-bit inte rle a ved tx data bus requires spi interf ace to co nfi g ur e; si m i l a r t o a d 98 62 data inte rface 4 .com u datasheet
AD9863 rev. a| page 24 of 40 table 11 describes AD9863 pin function (when mode pins are used) relative to i/o mode and for half-duplex modes, whether transmitting or receiving. table 11. AD9863 pin function vs. interface mode (no spi cases) 1 mode name u12 bus l12 bus iface1 iface2 iface3 fd interleaved tx data interl eaved rx data txsync buffere d rx clock buffered tx clock hd12 (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high 12/ 24 pin control tied high buffered tx clock hd12 (tx/ rx = low) msb = rxsync others = three-state interleaved rx data tx/ rx = tied low 12/ 24 pin control tied high buffered rx clock hd24 (tx/ rx = high) tx_a data tx_b data tx/ rx = tied high 12/ 24 pin control tied low buffered tx clock hd24 (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low 12/ 24 pin control tied low buffered rx clock clone mode (tx/ rx = high) x x x x x clone mode (tx/ rx = low) x x x x x 1 clone mode not available without spi. table 12 describes AD9863 pin function (when spi programming is used ) relative to flexible i/o mode and for half-duplex modes, whether transmitting or receiving. table 12. AD9863 pin function vs. interface mo de (configured through the spi registers) mode name u12 bus l12 bus iface1 iface2 iface3 fd interleaved tx data in terleaved rx data txsync buffered system clock buffered tx clock hd12, tx mode (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high optional buffered system clock buffered tx clock hd12, rx mode (tx/ rx = low) msb = rxsync other = three-state interleaved tx data tx/ rx = tied low optional buffered system clock buffered rx clock hd24, tx mode (tx/ rx = high) tx_a data tx_b data tx/ rx = tied high optional buffered system clock buffered tx clock hd24, rx mode (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low optional buffered system clock buffered rx clock clone mode, tx mode (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high optional buffered system clock buffered tx clock clone mode, rx mode (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low optional buffered system clock buffered rx clock summary of flexible i/o modes fd mode the full-duplex (fd) mode can be configured by using mode pins or with spi programming. using the spi allows additional configuration flexibility of the device. fd mode is the only mode that supports full-duplex, receive, and transmit concurrent operations. the upper 12-bit bus (u12) is used to accept interleaved tx data, and the lower 12-bit bus (l12) is used to output interleaved rx data. either the rx path or the tx path (or both) can be independently powered down using either (or both) the rxpwrdwn and txpwrdwn pins. fd mode requires interpolation of 2 or 4. the following notes provide a general description of the fd mode configuration. for more information, refer to table 15. note the following about the tx path in fd mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data. 4 .com u datasheet
AD9863 rev. a | page 25 of 40 ? buffered tx clock output (from iface3 pin) equals 2 the dac update rate; one rising edge per interleaved tx sample. note the following about the rx path in fd mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz. ? max adc sampling rate = 50 msps. ? the rx path output data rate is 2 the adc sample rate (interleaved). ? rx_a output when iface2 logic level = low. rx_b output when iface2 logic level = high. hd12 mode the half-duplex, 12-bit interleaved output mode, hd12, can be configured using mode pins or the spi. hd12 mode supports half-duplex only operations and can interface to a single 12-bit data bus with independent rx and tx synchronization pins (rxsync and txsync). both the u12 and l12 buses are used on the AD9863, but the logic level of the tx/ rx selector (controlled through iface1 pin) is used to disable and three-state the unused bus, allowing u12 and l12 to be tied together. the msb of the unused bus acts as the rxsync (during rx operation) or txsync (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin) switching, depending on which path is enabled. hd12 mode requires interpolation of 2 or 4. the following notes provide a general description of the hd12 mode configuration. for more information, refer to table 15. note the following about the tx path in hd12 mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? interleaved tx data accepted on u12 bus, l12 bus msb acts as txsync. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data. note the following about the rx path in hd12 mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz. ? max adc sampling rate = 50 msps. ? output data rate = 2 adc sample rate. ? interleaved rx data output from l12 bus. ? rx_a output when iface2 (or rxsync) logic level = low. rx_b output when iface2 (or rxsync) logic level = high. hd24 mode the half-duplex, 24-bit parallel output mode, hd24, can be configured using mode pins or through spi programming. hd24 mode supports half-duplex only operations and can interface to a single 24-bit data bus (two parallel 12-bit buses). both the u12 and l12 buses are used on the AD9863. the logic level of the tx/ rx selector (controlled through iface1 pin) is used to configure the buses as rx outputs (during rx operation) or as tx inputs (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin) switching, depending on which path is enabled. the following notes provide a general description of the hd24 mode configuration. for more information, refer to table 15. note the following about the tx path in hd24 mode: ? interpolation rate of 1, 2, or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 160 msps/channel with bypassed interpolation filters, 100 msps for 2 interpolation, or 50 msps for 4 interpolation. ? tx_a dac data is accepted from the u12 bus; tx_b dac data is accepted from the l12 bus. note the following about the rx path in hd24 mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz. ? max adc sampling rate = 50 msps. ? the rx_a output data is output on l12 bus; the rx_b output data is output on u12 bus. clone mode clone mode is an interface mode that provides a similar interface to the ad9860 when used in half-duplex mode. this mode requires spi to configure. clone mode provides a parallel rx data output (24 bits) while in rx mode, and it accepts interleaved tx data (12-bit) while in tx mode. both the u12 and l12 buses are used on the AD9863. the logic level of the tx/ rx selector (controlled through the iface1 pin) is used to configure the buses for rx outputs (during rx operation) or as tx inputs (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin), depending on which path is enabled. clone mode requires interpolation of 2 or 4. 4 .com u datasheet
AD9863 rev. a| page 26 of 40 the following notes provide a general description of the clone mode configuration. for more information, refer to table 15. note the following about the tx path in clone mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data. ? buffered tx clock output (from iface3 pin) uses one rising edge per interleaved tx sample. note the following about the rx path in clone mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz. ? max adc sampling rate = 50 msps. ? output data rate = adc sample rate, that is, two 12-bit parallel outputs per one buffer rx clock output cycle. ? the rx_a output data is output on l12 bus; the rx_b output data is output on u12 bus. configuring with mode pins the flexible interface can be configured with or without the spi, although more options and flexibility are available when using the spi to program the AD9863. mode pins can be used to power down sections of the device, reduce overall power consumption, configure the flexible i/o interface, and program the interpolation setting. the spi register map, which provides many more options, is presented in the configuring with spi section. mode pins/power-up configuration options mode pins provide various options that are configurable at power-up. control pins also provide options for power-down modes. the logic value of the configuration mode pins are latched when the device is brought out of reset (upon the rising edge of reset ). the mode pin names and functions are listed in table 13. table 14 provides a detailed description of the mode pins. table 13. mode pin names and functions pin name duration function rxpwrdwn permanent when high, digital clocks to the rx block are di sabled. analog circuitry that requires <10 s to power up is powered off. txpwrdwn permanent when high, digital clocks to tx block are disa bled (pll remains powered). analog circuitry that requires <10 s to power up is powered off. tx/ rx (iface1) permanent only for hd flex i/o interface when high, digital clocks to the tx block ar e disabled (pll remains powered to maintain output clock with an optional spi shutoff). tx analog circuitry remains powered up unless tx_pwrdwn is asserted. when low, digital clocks to rx block are disa bled. rx analog circuitry remains powered up unless rx_pwrdwn is asserted. adc_lo_pwr defined at reset or power-up when enabled, this bit scales the adc power-down by 40%. spi_bus_enable (spi_cs) defined at reset or power-up this function is controlled th rough the spi_cs pin. this pin must remain low to maintain mode pin functionality (the spi port remains no nfunctional). this pin must be high when coming out of reset to enable the spi. fd/ hd defined at reset or power-up configures the flex i/o for fd or hd mode. this control applies on ly if the spi bus is disabled. 12/ 24 only valid for hd mode defined at reset or power-up if the flex i/o bus is in hd mode, this bit is used to configure para llel or interleaved data mode. this control applies only if the spi bus is disabled. interp0 and interp1 defined at reset or power-up the interp1 and interp0 bi ts configure the pll and the interpol ation rate to 1 [00], 2 [01], or 4 [10]. this control applies only if the spi bus is disabled. 4 .com u datasheet
AD9863 rev. a | page 27 of 40 table 14. mode pin names and descriptions pin name description adc_lo_pwr adc low power mode option. adc_lo_pwr is latched during the rising edge of reset . logic low results in adc operation at nominal power mode. logic high results in the adc consuming 40% less power than the nominal power mode. fd/ hd (sdo) for flex i/o configuration, this contro l applies only if the spi bus is disabled. fd/ hd (sdo) is latched during the rising edge of reset . logic low setting identifies that the dut flex i/o port will be configured for half-duplex operation. 12/ 24 (iface2) is also latched during the rising edge of reset to identify interleaved data mode or parallel data mode. logic low indicates that the flex i/o will configure itself for parallel data mode. logic high indicates that the flex i/o will configure itself for interleaved data mode. 12/ 24 for flex i/o configuration, the 12/ 24 pin control applies only if the spi bus is disabled and the device is configured for hd mode. 12/ 24 is latched during the rising edge of reset . 12/ 24 (iface2) is used to identify interlea ved data mode or pa rallel data modes. logic low indicates that the flex i/o will configure itself for hd24 mode. logic high indicates that the flex i/ o will configure itself for hd12 mode. spi_bus_enable (spi_cs) spi_cs is latched during the rising edge of reset . logic low results in the spi being disabled; spi_dio, spi _clk, and spi_sdo act as mode pins configuration pins. logic high results in the spi being fully operational; some mode pins will be disabled. interp0 and interp1 interpolation/pll factor configuration. this co ntrol applies only if the spi bus is disabled. spi_dio (interp1) and spi_clk (interp0) configure the tx pa th for 1 [00], 2 [01], or 4 [10] interpolation and also enable the pll of the same multiplication factor. rxpwrdwn power-down control. rxpwrdwn logic level cont rols the power-down function of the rx path. logic low results in the rx path operating at normal power levels. logic high disables the adc clock and disables so me bias circuitry to re duce power consumption. txpwrdwn power-down control. txpwrdwn logic level cont rols the power-down function of the tx path. logic low results in the tx path operating at normal power levels. logic high disables the dac clocks and disables so me bias circuitry to reduce power consumption. tx/ rx power-down control. tx/ rx pin enables the appropriate tx or rx path in the half-duplex mode. logic low disables the tx path and enables the rx path. logic high disables the rx pa th and enables the tx path. 4 .com u datasheet
AD9863 rev. a| page 28 of 40 configuring with spi the flexible interface can be configured with register settings. using the register allows more device programmability. table 1 5 shows the required register writes to configure the AD9863 for fd, optional fd, hd24, optional hd24, hd12, optional hd12, and clone modes . note that for modes that use interleaved data buses, enabling 2 or 4 interpolation is required. table 15. registers for configuring spi register address setting description fd, mode 1 register 0x01 [7:5] [000] clk_ mode. configures timing mode. register 0x14 [4] high spifd/ hd . configures fd mode. register 0x14 [2] high spib12/ 24 . configures fd mode. register 0x13 [1:0] [01] or [10] interpolation control. configures 2 or 4 interpolation. optional fd, mode 2 register 0x01 [7:5] [001] clk_ mode. configures timing mode. register 0x14 [4] high spifd/ hd . configures fd mode. register 0x14 [2] high spib12/ 24 . configures fd mode. register 0x13 [1:0] [01] or [10] interpolation control. configures 2 or 4 interpolation. hd24, mode 4 register 0x01 [7:5] [000] clk_ mode. configures timing mode. register 0x14 [4] low spifd/ hd . configures hd mode. register 0x14 [2] low spib12/ 24 . configures hd24 mode. register 0x13 [1:0] [00], [01], or [10] interpolation control. configures 1, 2, or 4 interpolation. optional hd24, mode 5 register 0x01 [7:5] [011] clk_ mode. configures timing mode. register 0x14 [4] low spifd/ hd . configures hd mode. register 0x14 [2] low spib12/ 24 . configures hd24 mode. register 0x13 [1:0] [00], [01], or [10] interpolation control. configures 1, 2, or 4 interpolation. hd12, mode 7 register 0x01 [7:5] [000] clk_ mode. configures timing mode. register 0x14 [4] low spifd/ hd . configures hd mode. register 0x14 [2] high spib12/ 24 . configures hd12 mode. register 0x13 [1:0] [01] or [10] interpolation control. configures 2 or 4 interpolation. optional hd12, mode 8 register 0x01 [7:5] [101] clk_ mode. configures timing mode. register 0x14 [4] low spifd/ hd . configures hd mode. register 0x14 [2] high spib12/ 24 . configures hd12 mode. register 0x13 [1:0] [01] or [10] interpolation control. configures 2 or 4 interpolation. clone, mode 10 register 0x01 [7:5] [111] clk_ mode. configures timing mode. register 0x14 [0] high spiclo ne. configures clone mode. register 0x13 [1:0] [01] or [10] interpolation control. configures 2 or 4 interpolation. 4 .com u datasheet
AD9863 rev. a | page 29 of 40 spi register map registers 0x00 to 0x29 of the AD9863 provide flexible operation of the device. the spi allows access to many configurable optio ns. detailed descriptions of the bit functions are found in table 17. table 16. register map reg. name reg. add 7 6 5 4 3 2 1 0 general 0x00 sdio bidir lsb first soft reset clock mode 0x01 clk_mode [2:0] enable iface2 clkout inv clkout (iface3) power-down 0x02 tx analog tx digital rx digital pll power- down pll output disconnect rxa power- down 0x03 rx_a analog rx_a dc bias rxb power- down 0x04 rx_b analog rx_b dc bias rx power- down 0x05 rx analog bias rxref diffref vref rx path 0x06 rx_a twos complement rx_a clk duty rx path 0x07 rx_b twos complement rx_b clk duty rx path 0x08 rx ultralow power control rx ultralow power control rx path 0x09 rx ultralow power control rx ultralow power control rx ultralow power control rx path 0x0a rx ultralow power control rx ultralow power control rx ultralow power control tx path 0b dac a offset [9:2] tx path 0c dac a offset [1:0] dac a offset direction tx path 0d dac a coarse gain control dac a fine gain [5:0] tx path 0e dac b offset [9:2] tx path 0f dac b offset [1:0] dac b offset direction tx path 10 dac b coarse gain control dac b fine gain [5:0] tx path 11 txpga gain [7:0] tx path 12 txpga slave enable txpga fast update i/o configuration 13 tx twos complement rx twos complement tx inverse sample interpolation control [1:0] i/o configuration 14 dig loop on spifd/ hd spi tx/ rx spib12/ 24 spi io control spiclone clock 15 pll bypass adc clock div alt timing mode pll div5 pll multiplier [2:0] clock 16 pll to iface2 pll slow 4 .com u datasheet
AD9863 rev. a| page 30 of 40 table 17. register bit descriptions register bit description register 0x00: general bit 7: sdio bidir (bidirectional) default setting is low, which indicates that the sp i serial port uses dedicate d input and output lines (4-wire interface), sdio pins and sdo pins, respectively. setting this bit high configures the serial port to use the sdio pin as a bidirectional data pin. bit 6: lsb first default setting is low, which indicates msb fi rst spi port access mode. setting this bit high configures the spi port access to lsb first mode. bit 5: soft reset writing a high to this register resets all the regi sters to their default values and forces the pll to relock to the input clock. the soft reset bit is a one-shot register and is cleared immediately after the register write is completed. register 0x01: clock mode bit 7 to bit 5: clk_mode these bits represent the clocking interface for th e various modes. setting 000 is default. setting 111 is used for clone mode. refer to the summary of fl exible i/o modes section for a definition of clone mode. setting mode 000 standard fd, hd12, hd24 clock (modes 1, 4, 7) 001 optional fd timing (mode 2) 010 not used 011 optional hd24 timing (mode 5) 100 not used 101 optional hd12 timing (mode 8) 110 not used 111 clone mode (mode 10) bit 2: enable iface2 clkout enables the iface2 port to be an o utput clock. also inverts the iface2 output clock in full-duplex mode. bit 1: inv clkout (iface3) inver ts the output clock on iface3. register 0x02: power-down bit 7 to bit 5: tx analog (power-down) three options are available to reduce analog powe r consumption for the tx channels. the first two options disable the analog output from tx cha nnel a or b independently, and the third option disables the output of both channels and reduces the power consumption of some of the addi- tional analog support circuitry for maximum power savings. with all three options, the dac bias current is not powered down, so recovery times are fa st (typically a few clock cycles). the list below explains the different modes and settings used to configure them. power-down option bits setting [7:5] power-down tx a channel analog output [1 0 0] power-down tx b channel analog output [0 1 0] power-down tx a and tx b analog outputs [1 1 1] bit 4: tx digital (power-down) default is low, which enables the digital section of the transmit path to operate as programmed through other registers. by setting this bit high, the digital blocks are not clocked to reduce power consumption. when enabled, th e tx outputs are static, holdin g their last update values. bit 3: rx digital (power-down) setting this bit high powers down the digital section of the receive path of the chip. typically, any unused digital blocks are automatically powered down. bit 2: pll power-down setting this register bit high forces the clkin2 pll multiplier to a power-down state. this mode can be used to conserve power or to bypass the in ternal pll. to operate the AD9863 when the pll is bypassed, clkin2 must be supplied with a cl ock equal to the fastest tx path clock. bit 1: pll output disconnect setting this register bit high disconnects the pll o utput from the clock path. if the pll is enabled, it locks or stays locked as normal. register 0x03/04: rx power-down bit 7: rx_a analog/ rx_b analog (power-down) either adc or both adcs can be powered down by setting the appropriate register bit high. the entire analog circuitry of the rx channel is po wered down, including the differential references, input buffer, and the internal di gital block. the band gap reference remains active for quick recovery. bit 6: rx_a dc bias/ rx_b dc bias (power-down) setting either of these bits high powers down the input common-mode bias network for the respective channel and requires an input signal to be properly dc-biased. by default, these bits are low, and the rx inputs are self-biased to approx imately avdd/2 and accept an ac-coupled input. register 0x05: rx power-down bit 7: rx analog bias (power- down) setting this bit high powers down all analog bias ci rcuits related to the rece ive path (including the differential reference buffer). because bias circuits are powered down, there is an additional power saving, but also a longer recovery time relative to other rx power-down options. 4 .com u datasheet
AD9863 rev. a | page 31 of 40 register bit description bit 6: rxref (power-down) setting this register bit high powers down inte rnal adc reference circuits. powering down these circuits provides additional power saving over other power-down modes. the rx path wake-up time depends on the recovery of these references, typically of the order of a few milliseconds. bit 5: diffref (power-down) setting this bit high powers down the adcs diffe rential references, reft and refb. recovery time depends on the value of the reft and refb decoupling capacitors. bit 4: vref (power-down) setting this register bit high powers down the adc reference circuit, vref. powering down the rx band gap reference allows an external reference to drive the vref pin setting full-scale range of the rx paths. registers 0x06/0x07: rx path bit 5: rx_a twos complement/ rx_b twos complement default data format for the rx data is straight binary. setting this bit high generates twos complement data. bit 4: rx_a clk duty/rx_b clk duty setting either of these bits high enables the respec tive channels of the on-chip duty cycle stabilizer (dcs) circuit to generate the intern al clock for the rx block. this option is useful for adjusting for high speed input clocks with skewed duty cycles. the dcs mode can be used with adc sampling frequencies over 40 mhz. registers 0x08/0x09/0x0a: rx path rx ultralow power control bits set all bits high, in combination with assert ing the adc_lo_pwr pin, to reduce the power consumption of the rx path by a fourth of normal rx path power consumption. registers 0x0b/0x0c/0x0e/0x0f: tx path dac a/dac b offset these 10-bit, twos complement registers control a dc current offset that is combined with the tx a or tx b output signal. an offset current of up to 12% ioutfs (2.4 ma for a 20 ma full-scale output) can be applied to either differential pin on each channel. the offset current can be used to compensate for offsets that are present in an external mixer stage, reducing lo leakage at its output. the default setting is 0x00, no offset current. the offset cu rrent magnitude is set by using the lower nine bits. setting the msb high adds the offset current to the selected differential pin, while setting the msb low subtracts the offset value. dac a/dac b offset direction this bit determines to which diffe rential output pin the offset curre nt is applied for the selected channel. setting this bit low applie s the offset to the negative differential pin. setting this bit high applies the offset to the positive differential pin. register 0x0d/0x10: tx path bit 7, bit 6: dac a/dac b coarse gain control these register bits scale the full-scale output current (ioutfs) of either tx channel independently. iout of the tx channels is a function of the rset resistor, the txpga setting, and the coarse gain control setting. 00 output current scaling by 1/11 01 output current scaling by ? 10 no output current scaling 11 no output current scaling bit 5 to bit 0: dac a/dac b fine gain the dac output curve can be adjusted fractionally through the gain tr im control. gain trim of up to 4% can be achieved on each channel individually. the gain trim register bits are a twos complement attention control word. msb, lsb 100000 maximum positive gain adjustment 111111 minimum positive gain adjustment 000000 no adjustment (default) 000001 minimum negative gain adjustment 011111 maximum negative gain adjustment register 0x11: tx path bit 0 to bit 7: txpga gain this 8-bit, straight binary (bit 0 is the lsb, bit 7 is the msb) register control for the tx programmable gain amplifier (txpga). the txpga provides a 20 db continuous gain range wi th 0.1 db steps (linear in db) simultaneously to both tx channels. by default, this register setting is 0xff. msb, lsb 0000 0000 minimum gain scaling C20 db 1111 1111 maximum gain scaling 0 db register 0x12: tx path bit 6: txpga slave enable the txpga gain is controlled through register txpga gain setting and, by default, is updated immediately after the register write. if this bit is se t, the txpga gain update is synchronized with the falling edge of a signal applied to the txpwrd wn pin and is enabled during the wake-up from power-down. 4 .com u datasheet
AD9863 rev. a| page 32 of 40 register bit description bit 4: txpga fast update (mode) the txpga fast bit controls the update speed of the txpga. when fast update mode is enabled, the txpga provides fast gain settling within a few cloc k cycles, which may introd uce spurious signals at the output of the tx path. the de fault setting for this bit is lo w, and the txpga gives a smooth transition between gain settings. fast mode is enabled when this bit is set high. register 0x13: i/o configuration bit 7: tx twos complement the default data format for tx data is straight binary. set this bit high when providing twos complement tx data. bit 6: rx twos complement the default data format for rx data is straight binary. set this bit high when providing twos complement rx data. bit 5: tx inverse sample by default, the transmit data is sampled on the rising edge of the clkout. setting this bit high changes this, and the transmit data are sampled on the falling edge. bit 1, bit 0: interpolation control these register bits control the interpolation rate of the transmit path. the default settings are both bits low, indicating that both interpolation filt ers are bypassed. the msb and lsb are address bit 1 and address bit 0, respectively. setting binary 01 provides an interpolation rate of 2; binary 10 provides an interpolation rate of 4. register 0x14: i/o configuration bit 5: dig loop on when enabled, this bit enables a digital loop-ba ck mode. the digital loop-back mode provides a means of testing digital interfaces and functionali ty at the system level. in digital loop-back mode, the full-duplex interface must be enabled. (r efer to the flexible i/o interface options section.) the device accepts data from the digital input bus a ccording to the fd mode timing, and the data is processed by using the tx digital path (including any enabled interpolation filter). the processed data is then output fr om the rx path bus. bit 4: spifd/ hd control bit to configure full-duplex (high) or ha lf-duplex (low) interface mode. this register, in combination with the spib12/ 24 register, configures the interface mode of fd, hd12, or hd24. the register setting is ignored for clone mode operation . by default, this regist er is set high, and the device is in fd mode. bit 3: spitx/ rx control bit for transmit or receive mode for the half-duplex clock modes. high represents tx and low represents rx. bit 2: spib12/ 24 control bit for 12-bit or 24-bit modes. high represents 12-bit mode and low represents 24-bit mode. bit 1: spi io control use in conjunction with spitx/ rx [register14, bit 3] to override external tx/ rx pin operation. bit 0: spiclone set high when in clone mode (see flexible i/o interface options section for definition of clone mode). clk_mode should also be set to bi nary 111, such as [register 01[7:5] = 111. register 0x15: clock bit 7: pll_bypass setting this bit high bypasses the pll. when bypassed, the pll remains active. bit 5: adc clock div by default the adcs are driven directly from clkin1 in normal timing operation or from the pll output clock in the alternative timing operation. this bit is used to divide the source of the adc clock prior to the adcs. the default setting is low and performs no division. setting this bit high divides the clock by 2. bit 4: alt timing mode table 5 describes two timing modes: the normal t iming operation mode and the alternative timing operation mode. the default configuration is norm al timing mode, and the clkin1 drives the rx path. in alternative timing mode, the pll output is used to drive the rx path. the alternative operation mode is configured by setting this bit high. bit 3: pll div5 the output of the pll can be divided by 5 by setting this bit high. by default, the pll directly drives the tx digital path with no division of its output. bit 2 to bit 0: pll multiplier these bits control the pll multiplication factor. a de fault setting is binary 000, which configures the pll to 1 multiplication factor. th is register, in combination with the pll div5 register, sets the pll output frequency. the programmabl e multiplication factors are 000 1 001 2 010 4 011 8 100 16 101 to 111 not used register 0x16: clock bit 5: pll to iface2 setting this bit high switches the iface2 output sign al to the pll output clock. it is valid only if register 0x01, bit 2 is enabled or if full-duplex mode is configured. bit 2: pll slow changes the pll loop bandwidth; changes pr ofile of the phase noise generated from the pll clock. 4 .com u datasheet
AD9863 rev. a | page 33 of 40 programmable registers the AD9863 contains internal registers that are used to configure the device. a serial port interface provides read/write access to the internal registers. single-byte or dual-byte transfers are supported, as well as msb first or lsb first transfer formats. the AD9863s serial interface port can be configured as a single pin i/o (sdio) or as two unidirectional pins for in/out (sdio/sdo). the serial port is a flexible, serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. general operation of the serial interface by default, the serial port accepts data in msb first mode and uses four pins: sen, sclk, sdio, and sdo, by default. sen is a serial clock enable pin; sclk is the serial clock pin; sdio is a bidirectional data line; and sdo is a serial output pin. sen is an active low control gating read and write cycles. when sen is high, sdo and sdio go into a high impedance state. sclk is used to synchronize spi reads and writes at a maximum bit rate of 30 mhz. input data is registered on the rising edge, and output data transitions are registered on the falling edge. during write operations, the registers are updated after the 16th rising clock edge (and 24th rising clock edge for the dual-byte case). incomplete write operations are ignored. sdio is an input data only pin by default. optionally, a 3-pin interface may be configured using the sdio for both input and output operations and three-stating the sdo pin. refer to the sdio bidir bit in register 0x00 shown in table 17. sdo is a serial output data pin used for readback operations in 4-wire mode and is three-stated when sdio is configured for bidirectional operation. there are two phases to a communication cycle with the AD9863. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9863, coincident with the first eight sclk rising edges. the instruction byte provides the AD9863 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (one or two), and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the AD9863. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the AD9863 and the system controller. phase 2 of the communication cycle is a transfer of one or two data bytes as determined by the instruction byte. normally, using one communication cycle in a multibyte transfer is the preferred method; however, single byte communication cycles are useful to reduce cpu overhead when register access requires only one byte. an example of this is to write the AD9863 power-down bits. all data input to the AD9863 is registered on the rising edge of sclk. all data is driven out of the AD9863 on the falling edge of sclk. instruction byte the instruction byte contains the information shown in table 18, and the bits are described in detail after the table. table 18. instruction byte msb d6 d5 d4 d3 d2 d1 lsb r/ w 2/ 1 byte a5 a4 a3 a2 a1 a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates a read op eration. logic low indicates a write operation. 2/ 1 byte bit 6 of the instruction byte determines the number of bytes to be transferred during the data transfer cycle of the communication cycle. logic high indicates a 2-byte transfer. logic low indicates a 1-byte transfer. a5, a4, a3, a2, a1, a0 bit 5 to bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communication cycl e. for 2-byte transfers, this address is the starting byte address. the second byte address is automatically decremented when the interface is configured for msb-first transfers. for lsb-firs t transfers, the address of the second byte is automatically incremented. table 19. serial port interface timing maximum sclk frequency (f sclk ) 40 mhz minimum sclk high pulse width (t pwh ) 12.5 ns minimum sclk low pulse width (t pwl ) 12.5 ns maximum clock rise/fall time 1 ms data to sclk timing (t ds ) 12.5 ns data hold time (t dh ) 0 ns 4 .com u datasheet
AD9863 r e v. a| pa g e 34 of 4 0 wr i t e o p e r a t i o n s th e s p i wr i t e o p era t io n uses th e in s t r u c t i o n h e ader t o co n f i g - ur e a 1-b y t e o r 2-b y t e r e g i s t e r wr i t e usin g t h e 2/ 1 by t e s e t t i n g . th e in s t r u c t io n b y t e f o l l o w e d b y t h e r e g i s t er da t a is wr i t t e n se ri all y i n t o th e d e v i ce th r o ugh th e s d i o p i n o n ri s i n g ed g e s o f th e i n t e rfa c e c l oc k , sc l k . t h e d a ta ca n be tra n s f e r r e d m s b fi r s t o r l s b fi r s t , d e p e n d i n g o n t h e s e t t i n g o f t h e l s b - fi r s t r e g i s t er b i t. th e wr i t e o p e r a t io n is t h e sa m e , r e ga r d les s o f s d i o b i dir r e gis t er s e t t in g. f i gur e 52 t o f i g u r e 54 a r e e x a m p l e s o f wr i t in g da ta in t o th e d e v i c e . fi g u r e 5 2 s h ow s a 1 - by te w r it e i n m s b - f i r s t m o d e ; fi g u r e 5 3 s h ow s a 2 - by t e w r it e i n m s b - f i r s t mo d e ; a n d fi g u r e 54 s h ow s a 2 - by t e w r it e i n l s b - f i r s t m o d e . n o t e t h e dif f er en ces b e tw e e n ls b- a n d ms b- f i rst m o d e s: b o t h t h e in st r u c t i o n h e ader a n d da t a a r e r e vers e d , a n d t h e s e co n d da t a b y te reg i ster l o c a t i on i s di f f eren t . i n t h e de f a u l t m s b - f i rst m o de, t h e s e co n d da t a b y te is wr i t ten to a de cr em en te d r e g i st er addr es s. i n ls b- f i rst m o de, t h e s e co n d da t a b y te is wr i t t e n t o a n in cr em en t e d r e g i s t er add r es s. instruction header register data t s t ds t dh t hi t lo t clk t h don't care don't care 2/1 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care sen s cl k sdio r/w 03604-0-087 f i gure 52. 1-b y te s e ri al r e gis t er w r ite in msb - f i rs t m o de t h t s t ds t dh t hi t lo t clk sen s clk sdio 03604-0-088 don't care don't care a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w 2/1 don't care don't care instruction header (register n) register (n) data register (n?1) data f i g u re 53. 2-b y t e s e ri al r e g i s t er w r ite in m s -f irs t m o d e t h t s t ds t dh t hi t lo t clk sen sclk sdio 03604-0-089 don't care don't care don't care don't care instruction header (register n) register (n) data register (n+1) data a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 r/w 2/1 f i gure 54. 2-b y te s e ri al r e gis t er w r ite in lsb - f i rs t m o de 4 .com u datasheet
AD9863 rev. a | page 35 of 40 re a d o p er ati o ns t h e re a d b a c k of re g i ste r s c a n b e a s i ng l e or du a l d a t a b y te o p era t ion. th e r e ad back can be co nf igur ed t o us e 3-wir e o r 4-w i r e an d ca n b e fo r m a tte d w i t h ms b f i rst o r ls b f i rst. t h e in st r u c t io n h e a d er is wr i t ten t o t h e de vic e ei t h e r ms b o r ls b f i rs t (dep e ndi n g o n t h e m o de) fol l o w e d b y t h e 8-b i t o u t p u t da t a , a ppropr i a t ely m s b or l s b j u st i f i e d. by d e f a u l t , t h e output d a t a is s e n t to t h e de dic a te d o u t p u t p i n (s d o ). thre e- wir e o p er a t i o n ca n be co nf igured b y s e t t in g t h e s d i o b i dir r e g i s t er . i n 3 - wir e m o de, t h e s d io p i n wi l l b e com e an o u t p u t pi n a f ter r e ceiving t h e 8 - b i t i n s t r u c t io n h e ader w i t h a r e ad b a ck r e q u es t. f i g u re 5 5 s h o w s 4 - w i re spi re a d w i t h m s b f i r s t ; f i g u re 5 6 sh o w s 3 - w i re re a d w i t h m s b f i r s t ; a n d fi g u re 5 7 sh o w s 4 - w i re r e ad wi t h ls b f i rs t. t h t s t ds t dh t hi t lo t clk t dv sen sclk sdio sdo 03604-0-090 don't care don't care don't care don't care don't care don't care instruction header output register data a5 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r/w 2/1 f i gure 55. 1-b y te s e ri al r e gis t er r e ad back in msb f i rs t mode , sdio bid i r bit s e t l o gic l o w (d efault, 4- w i r e m o de) sen sclk sdio 03604-0-091 don't care don't care don't care a5 a4 a3 a2 a1 a0 r/w 2/1 don't care d7 d6 d5 d4 d3 d2 d1 d0 t s t ds t dh t hi t lo t clk t dv t h output register data instruction header f i gure 56. 1-b y te s e ri al r e gis t er r e ad back in msb f i rs t mode , sdio bid i r bit s e t l o gic high ( d efault, 3- w i r e m o de) sen sclk sdio sdo 03604-0-092 don't care don't care don't care a0 a1 a2 a3 a4 a5 r/w 2/1 don't care don't care don't care d0 d1 d2 d3 d4 d5 d6 d7 t s t ds t dh t hi t lo t clk t dv t h output register data instruction header f i gure 57. 1-b y te s e ri al r e gis t er r e ad back in lsb f i rs t mode , sdio bid i r bit s e t l o gic l o w (d efault, 4- w i r e m o de) 4 .com u datasheet
AD9863 rev. a| page 36 of 40 clock distribution block theory/description the AD9863 uses a pll clock multiplier circuit and an internal distribution block to generate all required clocks for various timing configurations. the AD9863 has two independent input clocks, clkin1 and clkin2. the clkin1 is primarily used to drive the rx adcs path. the clkin2 is primarily used to drive the txdacs path. there are many options for configuring the clock distribution block, which are programmed through internal register settings. the clock distribution block diagram section describes the timing block diagram breakdown, followed by the data timing for the different data interface options. the clock distribution block contains a pll, which includes an optional output divide-by-5 circuit, an adc divide-by-2 circuit, multiplexers, and other digital logic. there are two main methods of configuring the rx path timing of the AD9863: normal timing mode and alternate timing mode, which are controlled through register 0x15, bit 4. in normal timing mode, the rx path clock is driven directly from the clkin1 input, and the tx path is driven by a clock derived from clkin2 multiplied by the on-chip pll. in alternative timing mode, the clkin2 drives the pll circuitry, and the pll output clock drives both the rx path clock and tx path clock. because alternate timing mode uses the pll to derive the rx path clock, the adc performance may degrade slightly. this degradation is due to the phase noise from the pll, although typically it is only noticeable in undersampling applications when the input signal is above the first nyquist zone of the adc. the pll can provide 1, 2, 4, 8, and 16 multiplication or can be bypassed and powered down through register pll bypass [register 0x15, bit 7] and through register pll power- down [register 0x02, bit 2]. the pll requires a minimum input clock frequency of 16 mhz and needs to provide a minimum pll output clock of 32 mhz. this limit applies to the pll output prior to the optional divide-by-5 circuitry. for clock frequencies below these limits, the pll must be bypassed. the pll maximum output frequency before the divide-by-5 circuitry is 350 mhz. table 20 shows the input and output clock rates for all the multiplication settings. table 20. pll input and output minimum and maximum clock rates pll setting clkin2 input (min/max) (mhz) pll output clock (min/max) (mhz) 1 (pll bypassed) 1 /200 1 /200 1 (pll enabled) 32 /200 32 /200 2 16 /100 32 /200 4 16 /50 64 /200 8 16 /25 128 /200 1/5 1 32 /200 6.4 /40 2/5 1 16 /175 6.4 /70 4/5 1 16 /87.5 12.8 /70 8/5 1 16 /43.75 25.6 /70 16/5 1 16 /21.875 51.2 /70 1 indicates pll output divide-by-5 circuit enabled. clock distribution block diagram the clock distribution block diagram is shown in figure 58 . an output clock formatter configures the output synchronization signals, iface1, iface2, and iface3. these interface pin signals depend on clock mode setting, data i/o configuration, and other operational settings. clock mode and data i/o configuration are defined in register settings of clk_mode, spifd/ hd , and spib 12/ 24 . table 21 shows the configuration of the iface1, iface2, and iface3 pins relative to clock mode. for half-duplex cases, the iface1 pin is an input that identifies if the device is in rx or tx operation mode. the clock mode is used to specify the timing for each data interface operation mode, presented in detail in the flexible i/o interface options section. the t and r extensions after half-duplex modes 4 and 5, modes 7 and 8, and mode 10 in table 21 indicate that the device is in transmit or receive operation mode. the default clock mode setting [register 0x01, bit 5 to bit 7, clk_mode] of 000 configures clock mode 1 for the full-duplex operation, mode 4 for half- duplex 24 operation, and mode 7 for half-duplex 12 operation. mode 2, mode 5, mode 8, and mode 10 are optional timing configurations for the AD9863 and can be programmed through register 0x01 clk_mode. 4 .com u datasheet
AD9863 rev. a | page 37 of 40 03604-0-093 rx digital block rx path tx digital block tx path iface2 iface3 output clock formatter clkin1 1 2 3 4 5 6 50mhz max 1, 2 1, 2, 4, 8, 16 1, 5 1. alternate timing mode: reg 0x15, bit 4 2. pll multiplication setting: reg 0x15, bits 2 ? 0 3. pll output divide by 5; reg 0x15, bit 3 4. rx path divide by 2: reg 0x15, bit 5 5. pll bypass path: reg 0x15, bit 7 6. interp control, tx/rx inv iface3, clk mode, inv iface2, fd/hd, 12/24 clkin2 f i gure 58. cl ock d i s t ributi on b l o c k d i a g r a m table 21. i n terface pin s (iface1, iface2, iface3) con f iguration definition for flexible in terface operation clock m o d e p i n 1 2 4 t 4 r 5 t 5 r 7 t 7 r 8 t 8 r 1 0 t 1 0 r full-duplex half-duplex, 24- bit half-duplex, 12- bit clone m o d e clkin1, c l k i n 2 i n d e p e n d e n t internally tied to gether independent internally t i ed to gether independent internally t i ed to gether independent iface1 tx sync tx / rx tx / rx tx / rx iface2 b u f f _ c l k i n 1 r x s y n c optiona l clkou t optional clkou t optiona l clkout iface3 t x clock tx clock rx clock tx clock rx clock tx clock rx clock tx clock rx clock tx clock rx clock the tx clo c k o u t p u t f r e q ue n c y dep e n d s on w h et her t h e da t a is i n i n te rl e a ve d or p a r a l l el ( n oni n te rl e a ve d) c o n f i g u r a t i o n. m o d e s 1, 2, 7, 8, a nd 10 us e tx in t e rle a v e d da t a and r e q u ir e ei t h er 2 o r 4 in t e r p ola t io n t o b e enab le d . ? d a c u p da te ra te = clki n2 pll s e t t in g . ? n o nin t er lea v e d t x da t a c l o c k f r eq uen c y = clkin2 p ll se t t i n g 1 / (i n t er po l a ti o n ra t e ). ? i n ter l ea ved t x da ta c l o c k f r eq uen c y = 2 clkin2 p ll se t t i n g 1 / (i n t er po l a ti o n ra t e ). the rx clo c k do es n o t dep e n d o n w h et h e r t h e da t a is in te rle a ve d o r p a r a l l el, b u t i t do es dep e n d s on t h e co nf igur a t ion o f t h e t i mi n g mo de: n o r m a l o r a l ter n a t i ve. ? n o r m a l t i m i ng mo d e , r x cl o c k f r e q u e nc y = c l k i n 1 ad c di v fac t o r (if ena b led). ? a l t e r n a t iv e t i m i ng m o d e , r x cl o c k f r e q u e nc y = c l k i n 2 p ll set t in g ad c div fac t o r (if ena b led). a n opt i on a l c l k o u t f r om i f a c e 2 i s a v ai l a b l e a s a st a b l e sys t em clo c k r u nnin g a t t h e cl kin1 f r e q ue n c y o r t h e txd a c u p da te ra te , w h i c h is e q u a l t o c l kin2 pll s e t t in g . s e t t i n g t h e ena b le if a c e2 cl k o u t r e g i s t er [reg is t e r 0x0 1 , bi t 2] ena b les th e if a c e2 o p t i o n al c l o c k o u t p u t . i n fd m o de th e if a c e2 p i n a l wa y s ac t s as a clo c k o u t p u t ; t h e ena b le if a c e 2 p i n can b e us ed t o in v e r t t h e if a c e2 o u t p u t . c o nfigur ation the AD9863 t i min g f o r the tra n smi t p a th and f o r th e r e cei v e p a t h d e p e nd o n t h e mo de s e t t ing a nd va r i o u s p r o g r a mma b l e o p ti o n s. th e r e gi s t e r s th a t a f f e ct th e o u t p u t c l o c k ti mi n g a n d da ta i n p u t / o u t p u t ti mi n g a r e cl k _ m o de [2: 0 ], e n a b le if a c e2 cl k o u t , i n v cl k o u t (if a ce3), tx in v e rs e s a m p le , in t e r p ol a t ion co n t r o l, pll b y p a ss, ad c clo c k div , a l t t i ming m o de, pl l di v 5 , p ll m u l t i p lier , a nd p ll t o if a c e2. th e c l k_ m o de r e g i s t er is p r es en t e d p r e v i o us l y . t a b l e 22 sh o w s t h e ot h e r r e g i s t e r b i ts t h a t a r e us e d t o co nf igur e th e o u t p u t c l ock ti mi n g a n d d a ta la t c hi n g o p t i o n s a v a i la b l e in th e AD9863. 4 .com u datasheet
AD9863 r e v. a| pa g e 38 of 4 0 table 22. serial registers related to the clock distrib u tion block register name register addre ss, b i t ( s ) f u n c t i o n enable iface2 clkout register 0x01, bit 2 0: there is no clock output from iface2 pin, except in fd mode. 1: the iface2 pi n outputs a continuous refe rence clock from the pll outpu t . in fd mode, this inverts the iface2 output. inv clkout (iface3) register 0x01, bit 1 0: the iface3 cl ock output is not inverted. 1: the iface3 cl ock output is inverted. tx inverse sample register 0x13, bit 5 0: the tx path d a ta is latched relative to the out p ut tx clock rising edge. 1: the tx path d a ta is latched relative to the out p ut tx clock falling edge. interpolation control register 0x13, bit 1:0 sets interpolati o n of 1, 2, or 4 for the t x path. pll_bypass register 0x15, bit 7 0: pll block is used to generate system clock. 1: pll block bypasses generate system clock. adc clock div register 0x15, bit 5 0: adc clock rat e eq uals the rx path freq uency. 1: adc clock is one-half the rx path freq uency. alt timing mode register 0x15, bit 4 0: clki n1 is used to drive the rx path cloc k. 1: pll block output is used to dr ive the rx path clock. pll div5 register 0x15, bit 3 0: pll bl ock output clock is not divided down. 1: pll block output clock is divided by 5. pll m u ltiplier register 0x15, bit 2:0 s e t s m u l t i p l i c a t i o n f a c t o r o f t h e pll block t o 1 ( 000) , 2 (0 01) , 4 ( 0 1 0 ), 8 ( 0 1 1 ), or 1 6 x ( 1 0 0 ). pll to ifac e2 register 0x16, bit 5 0: if enable iface2 clkout register is set, ifac e2 outputs buffere d clkin. 1: if enable iface2 clkout register is se t, iface2 outputs buffere d pll ou tput clock. t r a n smi t (tx) t i min g r e q u ir es sp e c if ic s e t u p and h o l d t i m e s t o p r o p erl y la t c h da t a t h r o ug h t h e da t a in t e r f ace b u s. th e s e t i ming p a r a me te rs are sp e c i f i e d rel a t i v e to an i n te r n a l l y ge ne r a te d o u t p u t r e f e r e n c e c l o c k. the AD9863 has tw o in t e r f ace c l o c ks p r o v ided t h r o ug h t h e if a c e3 a nd if a c e2 p i ns. th e tra n smi t t i mi n g sp e c if ica t io n s an d s e t u p a nd h o l d t i m e s p r o v id e a mini m u m r e q u i r e d w i n d o w o f v a lid d a t a . se t u p ti m e ( t set u p ) is t h e t i m e re q u ir e d fo r d a t a t o ini t ia l l y s e t t le t o a valid log i c le v e l p r io r t o t h e r e la t i v e o u t p u t timin g e d ge . ho l d t i m e ( t ho l d ) i s th e tim e a f t e r th e o u t p u t tim i n g e d g e tha t valid da t a m u st r e ma in o n t h e da ta b u s t o b e p r o p erl y la t c hed . fi g u r e 5 9 s h ow s t setu p and t ho l d r e la t i v e t o if a c e3 fal l in g e d g e . n o t e t h a t in s o m e cas e s nega t i v e t i m e is sp e c if ie d , fo r exa m ple, wi t h t ho l d ti m i n g , whi c h m e a n s th a t t h e h o ld t i m e e d g e occur s b e f o re t h e rel a t i ve outp ut cl o c k e d ge. iface3 (clkout) tx data 03604-0-094 t setup t hold f i gu r e 5 9 . t x da ta t i m i n g dia g r a m t a b l e 23 sh o w s typ i c a l s e t u p and h o l d tim e s f o r th e AD9863 in t h e va r i o u s mo de co nf igur a t ion s . table 23. ty pical tx data la tch timing relat i ve to iface3 falling edge mode no. mode name t set u p (ns) t hold (ns) 1 fd 5 C2.5 2 optional fd 5 C2.5 4 hd24 5 C1.5 5 optional hd24 5 C1.5 7 hd12 5 C2.5 8 optional hd12 5 C2.5 10 clone 5 C1.5 r e ce i v e (r x) pa th d a ta i s o u t p u t a f t e r a r e f e r e n c e o u t p u t c l oc k ed g e . th e tim e d e la y o f t h e r x da ta r e la ti v e t o a r e f e r e n c e output cl o c k i s c a l l e d t h e output d e l a y , t od . the AD9863 has two p o s s i b le in t e r f ace c l o c ks p r o v ided thr o ug h t h e if a c e3 a n d if a c e2 p i n s . f i gur e 60 s h o w s t od r e la ti v e t o t h e if a c e3 r i sin g e d ge . n o t e t h a t in s o me cas e s nega t i v e t i m e is sp e c if ie d , w h ich m e a n s tha t t h e o u t p u t d a t a tra n si ti o n occ u r s p r i o r t o th e r e la ti v e output cl o c k e d ge. iface3 (clkout) rx data 03604-0-095 t od f i g u re 60. r x d a t a ti ming d i ag r a m 4 .com u datasheet
AD9863 rev. a | page 39 of 40 table 24 shows typical output delay times for the AD9863 in the various mode configurations. table 24. AD9863 rx data latch timing mode no. mode name t od data delay [ns] relative to: 1 fd +2.5 ns relative to iface2 rising edge +1 ns relative to iface3 rising edge 2 optional fd +1 ns relative to iface3 rising edge +2 ns iface2 (rxsync) relative to lsb 4 hd24 ?1.5 ns relative to iface3 rising edge 5 optional hd24 ?0.5 ns relative to iface3 rising edge 7 hd12 ?1.5 ns relative to iface3 rising edge 8 optional hd12 +0.5 ns relative to iface3 rising edge +0 ns u12 (rxsync) relative to lsb 10 clone +1.5 ns relative to iface3 rising edge configuration without serial port interface (using mode pins) the AD9863 can be configured using mode pins if a serial port interface is not available. this section applies only to configur ing the AD9863 without an spi. refer to the configuring with mode pins section of the data sheet for more information. when using the mode pin option, the pins shown in table 25 are used to configure the AD9863. table 25. using mode pin (spi disabled) to config ure timing (spi_cs, pin 64, must be tied low) clock mode interpolation setting pll setting fd/ hd pin 3 12/ 20 pin 17 interp1, interp0 pin 1, pin 2 mode 1 (fd) 2 4 2 4 1 n/a 1 0, 1 1, 0 mode 4 (hd24) 1 2 4 bypassed 2 4 0 0 0, 0 0, 1 1, 0 mode 7 (hd12) 2 4 2 4 0 1 0, 1 1, 0 1 pin 17 (iface2) is an output clock in fd mode. 4 .com u datasheet
AD9863 r e v. a| pa g e 40 of 4 0 outline dimensions * compliant to jedec standards mo-220-vmmd except for exposed pad dimension pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.45 0.40 0.35 0.30 0.25 0.18 7.50 ref 0.60 max 0.60 max * 7.25 7.10 sq 6.95 pin 1 indicator 0.25 min 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane exposed pad (b o t t o m view) f i gure 61. 6 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p _vq] 9 9 m m b o dy , v e r y thin q u ad (c p - 6 4 - 3 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option AD9863bcp-50 ? 40 c to +85 c 64-lead lfcsp_ vq cp-64-3 AD9863bcprl-5 0 ? 40 c to +85 c 64-lead lfcsp_ vq cp-64-3 AD9863bcpz-5 0 1 ? 40 c to +85 c 64-lead lfcsp_ vq cp-64-3 AD9863bcpzrl - 50 1 ? 40 c to +85 c 64-lead lfcsp_ vq cp-64-3 a d 9 8 6 3 - 5 0 e b e v a l u a t i o n boar d 1 z = pb-free part. ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03604C0 C 4/05(a) 4 .com u datasheet

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